A multi-chip module (MCM includes a substrate and first and second integrated circuit chips disposed on the substrate. The second IC chip includes transceiver circuitry configured to communicate with the first IC chip. The transceiver circuitry includes transmit circuitry having an inverter circuit to generate a first signal for transmission to the first IC chip along a signaling link. The signaling link includes a line termination impedance. Receiver circuitry includes a receiver circuit to receive a second signal from the first IC chip along the signaling link concurrently with transmission of the first signal along the signaling link. Hybrid circuitry is coupled to the transmit circuitry and to the receiver circuitry. The hybrid circuitry is configured to cancel a received component of the first signal. The hybrid circuitry includes a replica termination impedance that is configured in an open state.

A clock recovery circuit includes a clock detector configured to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, reverse channel data, or a combination of the clock reference data and the reverse channel data, and the clock detector configured to output a clock detect signal in response to detecting the clock reference data in the serial data stream; a phase lock loop including a first detector configured to receive the serial data stream and to detect phase and frequency; and a controller configured to receive the clock detect signal and to selectively enable the first detector based on the clock detect signal.

A device for synchronous serial data transmission over a differential data channel and a differential clock channel includes an interface controller having a clock generator, data controller, clock transmitter block and data receiver block. The clock generator generates a transmit clock signal which, during a data transmission cycle, includes a clock pulse train having a period. The clock generator is suitably configured such that, for data transmission cycles in a dynamic operating state in which a maximum occurring differential voltage of a differential clock signal is lower than a maximum differential voltage of the clock transmitter block, the clock generator sets a duration of a first clock phase of a first clock period of the clock pulse train to be longer than a first clock phase of following clock periods and shorter than a time duration required to reach the maximum differential voltage.

One embodiment relates to a transmitting device, a receiving device, and the like for preventing increases in the number of communication links, power consumption, and circuit layout area. The transmitting device includes a high-speed signal generator, a low-speed signal generator, and a signal superimposing unit. The high-speed signal generator generates a high-speed signal having a limited frequency band. The low-speed signal generator generates a low-speed signal having a frequency lower than the frequency band of the high-speed signal. The signal superimposing unit outputs a superimposed signal of the high-speed signal and the low-speed signal. The receiving device includes a signal separator and a recovery unit. The signal separator separates the received signal into the high-speed signal and the low-speed signal. The recovery unit performs frequency tracking based on the separated low-speed signal and performs phase tracking based on the separated high-speed signal.

This application discloses a clock synchronization system, including a quantum control processor (QCP) and N digital/analog mutual conversion devices, each digital/analog mutual conversion device including a frequency conversion module and a signal synchronization module that includes a D flip-flop (DFF). The QCP generates a global synchronization signal and reference clock signals; and transmits the global synchronization signal and a reference clock signal to the frequency conversion module and transmits the global synchronization signal to the signal synchronization module of each conversion device. The frequency conversion module performs frequency conversion processing on the reference clock signal to obtain a target clock signal, and generates a signal synchronization instruction according to the global synchronization signal; and transmits the signal synchronization instruction and the target clock signal to the signal synchronization module. The signal synchronization module performs, based on the global synchronization signal, signal synchronization on the target clock signal through the DFF.

A system and method for multi-rate synchronization of a digital sensor that provides a digital sensor output signal and a processor arrangement that processes the digital sensor output signal according to a processing algorithm and that provides a processor output signal, including operating the digital sensor to provide the digital sensor output signal with a first sample rate, and operating the processor arrangement to provide a processor output signal with a second sample rate. The second sample rate is an integer multiple of the first sample rate.

An apparatus is provided for converting the form in which a synchronisation request for a barrier synchronisation is provided. The synchronisation request is provided from a first synchronisation circuitry to a second synchronisation circuitry by asserting one of a set of separate signals that may each correspond to a bit in a register or a signal on a wire. The second synchronisation circuitry provides for the packetisation of the sync request by sending a packet comprising the sync request over a network to be received at a further subsystem.

A physical layer transceiver for a node in a wireline communication system includes receiver circuitry for receiving communications from a link partner on a first link path, transmitter circuitry for transmitting communications to the link partner on a second link path, and an energy-efficient Ethernet (EEE) controller for reducing power consumption on the first or second link path, when activity on that link path is reduced. In a low-power mode, there are periodic refresh intervals of a first duration, during which signals are received or transmitted, and, between the refresh intervals, quiet intervals of a second, longer, duration, during which transmission and reception of signals are avoided. The EEE controller detects a change in an environmental condition affecting that link path, and upon detection of that change, adjusts a parameter of the low-power mode on at least one of the first and second link paths.

Examples described herein include systems and methods for performing email synchronization in situations where mobile-device connectivity is lacking. The mobile device can send an SMS message to an email notification server requesting email synchronization and the email notification server can request synchronization with the email server associated with the user's email account. After receiving an email from the email server, the email notification server cart encrypt the email and break it into various chunks, with each chunk including a header having identifying information. The chunks can be transmitted as SMS messages to the mobile device, The email application can retrieve the SMS messages, decrypt them, and reconstruct the email. The email application can then display the email for the user.

According to one aspect there is provided an audio system 10 comprising a transmission unit 100 and a plurality of speaker units 110-1, 110-2, 10-N, wherein the transmission unit 100 comprises a controller 101 and a wireless communication interface 103 arranged for communication according to an IEEE 802.11 standard (WiFi™), wherein the controller 101 is configured to: receive an audio data package to be played back; and to transmit the audio data package to be played back over the wireless communication interface 103 utilizing the same protocol for the transmission of the audio data package and for synchronizing the playback of the audio data, and wherein each of plurality of the speaker units 110-1, 110-2, 10-N comprises a controller 111, a PCM 111-1, a speaker element 114 and a wireless communication interface 113 arranged for communication according to an IEEE 802.11 standard (WiFi™), wherein the controller 111 is configured to: receive the at least one data package to be played back through the wireless communication interface 113 and to cause audio represented by the received audio data package to be played back through the speaker element 114 by feeding the audio data to the PCM 111-1 being connected to the speaker element 114.