A slave apparatus (300) includes a clock extraction unit (310) and a time-point management unit (350). As long as the slave apparatus (300) receives serial data, the clock extraction unit (310) extracts a communication clock from the serial data being received. The time-point management unit (350) includes a timekeeper (351) driven based on the communication clock.

This disclosure contributes a Unified Clock which utilizes frequency alignment throughout network nodes for accurate time stamping and direct elimination of nodes residence delays from times originated in Grand Master (GM) and propagated downstream with PTP messages, wherein downstream slave nodes are maintaining local slave time (LST) delayed to the GM time by downstream links delays only and such links delays are estimated separately and added to the LST in order to derive Local Master Time (LMT) corresponding to the GM time.

There is described a system and method for configuring multiple PTP ports of a network device comprising an input component and a processor. A PTP port group, associated with a subset of PTP ports of the network device and with a PTP region, is identified. A PTP parameter set corresponding to the PTP port group is received and applied to each port of the subset of PTP ports associated with the PTP port group. A time exchange is performed for PTP capable devices within the PTP region. There is also described a PTP network device comprising a first transparent clock, a second transparent clock, and a boundary clock. The first transparent clock performs time exchange within the first PTP region. The second transparent clock performs time exchange within the second PTP region. The boundary clock performs time exchange between the first and second PTP regions.

There is described a Precision Time Protocol (“PTP”) transparent clock for inter-VLAN forwarding comprising a Layer 2 switch and a PTP module. The switch includes a first port associated with a first VLAN and a second port associated with a second VLAN. The switch detects a PTP frame at the first port and the PTP module receives the PTP frame. The switch forwards the PTP frame to the second port in response to the PTP module determining that the PTP frame is a forwardable frame. For another embodiment, the switch includes a ternary content-addressable memory (“TCAM”), and the PTP module configures the TCAM to include forwarding rules. The Layer 2 switch forwards the PTP frame to the second port in response to identifying a particular forwarding rule associated with forwarding the PTP frame.

Systems and methods are provided for master media clock recovery. In various embodiments, recovering a master media clock may comprise receiving clock reference format (CRF) packets carrying timestamps (Ts). Differences of Ts between adjacent CRF packets may be calculated, and an average difference of Ts between adjacent timestamps may be calculated. A recovered frequency of a master clock may be based on the calculated average difference of Ts between adjacent timestamps. The recovered frequency may be used to regulate a timing of, for example, a kernel module and/or a media application.

A second transmission path coupler has such a size that a signal width of a first signal that is generated by the second transmission path coupler at timings corresponding to a rising edge and a falling edge of an input signal to be input to a first transmission path coupler in a case where the input signal is transmitted to a position at which the first transmission path coupler and the second transmission path coupler perform an electric field and/or magnetic field coupling is substantially equal to or greater than a difference in a transmission delay amount corresponding to a gap of the first transmission path coupler.

A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal, and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.

Disclosed herein is a method and system for utilizing a digital data capture device in conjunction with a Bluetooth (BT) enabled mobile device for publishing data and multimedia content on one or more websites automatically or with minimal user intervention. A client application is provided on the BT enabled mobile device. In the absence of inbuilt BT capability, a BT communication device is provided on the digital data capture device. The BT communication device is paired with the BT enabled mobile device to establish a connection. The client application detects capture of data and multimedia content on the digital data capture device and initiates transfer of the captured data, multimedia content, and associated files. The digital data capture device transfers the captured data, multimedia content, and the associated files to the client application. The client application automatically publishes the transferred data and multimedia content on one or more websites.

A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.

A synchronization circuit, a semiconductor storage device, and a synchronization method provided herein, which are capable of performing synchronization on a small circuit scale, includes: a first delay circuit delaying a input synchronization signal by a first predetermined time to generate a first delay synchronization signal; a second delay circuit delaying the first delay synchronization signal by a second predetermined time to generate a second delay synchronization signal; a first synchronization circuit outputting a first output data generated by synchronizing the input data with the input synchronization signal; a second synchronization circuit outputting a second output data generated by synchronizing the input data with the first delay synchronization signal; and a resynchronization circuit resynchronizing the input data with the second delay synchronization signal to update the first output data to the first synchronization circuit when the first output data is inconsistent with the second output data.