A clock data recovery circuit detects illegal decisions for received data, accumulates a phase gradient for the data, determines a number of the illegal decisions in a configured window for receiving the data, and if the number of the illegal decisions exceeds a pre-defined number in the window, applies a sum of the accumulated phase gradient and a phase increment having a sign of the accumulated phase gradient to a clock circuit for the data receiver.

Provided are a Kramers—Kronig (KK) reception-based terahertz (THz) signal reception apparatus and a method for compensating a frequency offset using the same. A method of compensating for a frequency offset performed by a THz signal reception apparatus includes receiving, from a THz signal transmission apparatus, a THz signal including carrier signals corresponding to three different frequency bands, extracting, from the received THz signal, a reference carrier included in the THz signal or a sampling clock generated in a process of generating a data signal, and compensating for a frequency offset generated in a process of transmitting the THz signal by using the extracted reference carrier or sampling clock.

A carrier recovery unit is provided including: separation-and-output section that outputs separated symbol group formed into block; a priori state-estimation section that obtains a priori estimate acquired by estimating values processed this time from among values of intra-block frequency and central phase processed last time; provisional compensation section that provisionally compensates the phase of each separated symbol based on the a priori estimation phase; decision section that performs decision based on the reference signal for the symbol before decision, and obtains symbol after decision; error-estimation section that calculates the frequency and phase errors; a posteriori state-estimation section that obtains a posteriori estimate based on the frequency and phase errors; actual compensation section that actually compensates the phase based on the a posteriori estimation phase; and feedback processing section that feeds back the a posteriori estimate as the values processed last time to the a priori state estimation section.

A mobile communication device according to one embodiment includes a receiver, an imager, a detector, a determiner. The receiver configured to receive a frame including a first timing, a second timing, and first position information. The imager configured to capture the imaging target for a plurality of times. The detector configured to detect second position information, and third position information. The determiner determines whether or not the frame received by the receiver is a frame transmitted in tandem with an operation performed by the imaging target based on first to fourth timings. The corrector, when the determiner configured to determine that the frame received by the receiver is a frame transmitted in tandem with an operation performed by the imaging target, correct a timing of the clock based on the first to third position information and the first to fourth timings.

Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.

A serializer may be provided. The serializer may include a first data output circuit and a second data output circuit. The first data output circuit may provide first data to an output node in synchronization with a first phase clock and a second phase clock. The second data output circuit may provide second data to the output node in synchronization with the second phase clock and a third phase clock. The first data output circuit may perform a precharge operation or an emphasis operation for the second data output circuit, in synchronization with a third phase clock.

A communication device includes: a computing circuit, performing a J.sup.th power operation according to a first plurality of time-domain signals to generate a first plurality of computed signals; a transforming circuit, coupled to the computing circuit, transforming the first plurality of computed signals to a first plurality of frequency-domain signals according to a time-frequency transformation; a control circuit, coupled to the converting circuit, performing an absolute value operation on the first plurality of frequency-domain signals to generate a first plurality of output signals; a selecting circuit, coupled to the control circuit, selecting a maximum output signal satisfying a check condition from the first plurality of output signals; and a frequency estimating circuit, coupled to the selecting circuit, estimating a carrier frequency offset according to the maximum output signal.

A source component includes a clock source to generate a clock signal, a plurality of front-end driver circuits to transmit signals to a sink component over a plurality of data lanes of an interconnect, and a clock distribution circuit coupled to the clock source and the plurality of front-end driver circuits. The clock distribution circuit is to distribute a first clock pulse of the clock signal on a first data lane and a second clock pulse of the clock signal on a second data lane. A sink component is to recover the first clock pulse of the clock signal from the first data lane and the second clock pulse of the clock signal from the second data lane, wherein the clock recovery circuit includes clock reconstruction logic to reconstruct the clock signal from the first clock pulse and the second clock pulse.

Embodiments of the present invention may provide a system with a first and second circuit system separated by an electrical isolation barrier but provided in communication by at least one isolator device that bridges the isolation barrier. The first circuit system may include a communication system to transmit data across a common isolator device as a series of pulses, and the second circuit system may receive the series of pulses corresponding to the data. The second circuit system may include a detector coupled to the common isolator device to detect the received pulses, a oneshot to frame the received pulse(s), and a controller to reconstruct the data based on accumulated framed pulse(s). Therefore, noise induced spurious pulses outside the oneshot intervals may be ignored by the second circuit system providing improved noise immunity.

Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL.