The present invention achieves, using simple circuits, timing synchronization among ECUs of an electronic control device which is configured from a driver ECU, a sensor ECU, and an integrated ECU which are connected over a network. This electronic control device is provided with a driver ECU for driving various loads for vehicular control, a sensor ECU for sampling various sensor signals, and an integrated ECU which is connected to the driver ECU and sensor ECU over a network and calculates command values to the various loads in accordance with various sensor data, the electronic control device being characterized in that the driver ECU has timer D for generating internal timing, the sensor ECU has timer S for generating internal timing, and the integrated ECU has timer M serving as a reference for timer D and timer S.

A domain manager configured to manage and/or configure an audio-video (AV) system but not directly participate in networked media transmission or clock synchronization. The domain manager may include a database; an endpoint manager configured to communicate with the database, the endpoint manager being configured to setup and maintain secure connections to and from media devices and controllers; and at least one management module configured to communicate with the database and provide services to the media devices and controllers. In embodiments, the at least one management module may include at least one of a manager for managing credentials and grouping devices into domains, a device directory for managing device registrations and lookup, and an access controller for managing and/or evaluating access control policy.

The present invention provides a receiver including a sampling circuit, a data sampling point selection circuit and a determination circuit. The sampling circuit is configured to use a clock signal to sample an input signal to generate a sampled signal, wherein a frequency of the clock signal is greater than a frequency of the input signal. The data sampling point selection circuit is configured to filter start point data to generate a filtered start point data, and to generate a data sampling point by adding an offset to the filtered start point data, wherein the start point data corresponds to a time point that a sampled value of sampled signal starts to change. The determination circuit is configured to refer to a sampled value corresponding to the data sampling point in the sampled signal to determine a logical value of a digital output signal corresponding to the input signal.

A distributed hybrid algorithm that synchronizes the time and rate of a set of clocks connected over a network. Clock measurements of the nodes are given at aperiodic time instants and the controller at each node uses these measurements to achieve synchronization. Due to the continuous and impulsive nature of the clocks and the network, we introduce a hybrid system model to effectively capture the dynamics of the system and the proposed hybrid algorithm. Moreover, the hybrid algorithm allows each agent to estimate the skew of its internal clock in order to allow for synchronization to a common timer rate. We provide sufficient conditions guaranteeing synchronization of the timers, exponentially fast. Numerical results illustrate the synchronization property induced by the algorithm as well as its performance against comparable algorithms from the literature.

A computer-implemented method for data synchronization in a P2P ad hoc network includes retrieving network configuration information identifying a plurality of devices forming the P2P ad hoc network. A time offset between a local physical time at a first device and a local physical time of a second device is determined. A change in a data object of a plurality of data objects stored at a key-value store within the first device is detected, each of the data objects including a synchronization indicator. The data object change is communicated to at least the second device based on the synchronization indicator. Upon receiving confirmation from the at least the second device of receipt of the data object change, the network configuration information is updated with a. timestamp based on the time offset and indicative of the local physical time at the first device when the data object change was communicated.

A Bluetooth receiver has an RF front end which has a gain control input, the RF front end converting wireless packets into a baseband signal which is coupled to the input of an analog to digital converter (ADC). A clock generator provides a clock coupled to the ADC, and an AGC processor performs an AGC process to provide a gain which places the baseband symbols in a range that is less than 90% of the input dynamic range of the ADC. When in a connected state, the clock generator provides a clock which is slower than is required to complete the AGC process during a preamble interval, and the AGC process uses a few initial bits of the address field. The remaining bits of the address field is compared with the corresponding address bits of the receiver to determine whether to receive the packet.

A transmitter 10B always transmits a signal (data in which a dock is embedded) generated by the serializer 11 to the communication link. The receiver 20B includes a recovery circuit 22, a deserializer 23, a selector 25, and a training signal generator 32. The training signal generator 32 generates and outputs a training signal for frequency synchronization of the recovering operation of the recovery circuit 22. The selector 25 receives the signal from the transmitter 10B via the communication link and receives the training signal output from the training signal generator 32. The selector 25 selects and outputs either the received signal or the training signal according to the level of the lock signal output from the recovery circuit 22.

An input signal arranged in frames is received. The frames include a cyclic redundancy check (CRC) field including a number of bits having bit edges. A timing signal is generated to include adjustable duration waveforms at one of a first duration value and a second duration value. A CRC check determines the occurrence, over the duration, of a number of waveforms of the timing signal having their duration adjusted to one of the first duration value and the second duration value which corresponds to the number of bits. A check signal is produced having a pass/fail value. If pass, the duration of the waveforms in the timing signal is maintained adjusted to the one of the first duration value and the second duration value. If fail, the duration of the waveforms in the timing signal is re-adjusted to the other of the first duration value and the second duration value.

The present invention is to reduce detection of an erroneous edge caused by variation in a case of a sampling frequency that is not larger than a data transmission frequency. A semiconductor device includes: a data reception circuit configured to receive first data at first time and receive second data at second time; and an edge recognition circuit configured to set a range and detect an edge contained in the range. The edge recognition circuit includes a measurement circuit configured to measure a first period taken from the reception of the first data to the reception of the second data, and is configured to determine the range in which the edge contained in the data that is received by the data reception circuit is detected, on the basis of the first period.

An audio synchronization processing method is provided. The method includes the following steps: receiving an input request signal; in response to receiving the input request signal, starting performing a counting operation according to a basic clock signal; outputting an output request signal according to a sampling-clock signal; in response to outputting the output request signal, stopping performing the counting operation to obtain a counting value; determining whether synchronization has been achieved based on the counting value; and in response to determining that the synchronization has not been reached, adjusting a frequency of the sampling-clock signal according to the counting value.