A method of encoding input data includes receiving the input data that includes a plurality of input words including a first input word and a second input word, generating a plurality of converted words including a first converted word and a second converted word, the first converted word being based at least on the first input word, the second converted word being based on the first converted word and the second input word, identifying a key value based on the plurality of converted words, and generating a plurality of coded words based on the key value and the plurality of converted words.

A radio-head apparatus can comprise synchronization circuitry to receive transmission data and a phase correction signal. The synchronization circuitry can process the transmission data and the phase correction signal to generate digital transmitter (DTX) codes. The radio-head can further include transmission circuitry to combine the phase correction signal with transmission data codes to be provided to the DTX for transmission over an air interface. Other systems and apparatuses are described.

There is provided mechanisms for relative time error (TE) information distribution in a telecommunication network using a precision time protocol (PTP). A method is performed in a gateway device in a telecommunication network having hierarchical segments. The method comprises receiving TE information from a telecom grandmaster (T-GM) of the hierarchical segments. The method comprises preserving a total TE information of the received TE information. The method comprises resetting an accumulated path TE of the received TE information. The method comprises outputting an indication of the reset accumulated path TE and the preserved total TE information to a sub-segment of the hierarchical segments.

A hybrid receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. Depending on a baud rate of the serial data stream, either the digital receive circuit or the analog receiver circuit is activated to provide the desired performance and power consumption over the range of possible baud rates. The ADC-based receiver circuit may include multiple analog-to-digital converter circuits with different resolutions that can be selected for different baud rates.

The present invention is to reduce detection of an erroneous edge caused by variation in a case of a sampling frequency that is not larger than a data transmission frequency. A semiconductor device includes: a data reception circuit configured to receive first data at first time and receive second data at second time; and an edge recognition circuit configured to set a range and detect an edge contained in the range. The edge recognition circuit includes a measurement circuit configured to measure a first period taken from the reception of the first data to the reception of the second data, and is configured to determine the range in which the edge contained in the data that is received by the data reception circuit is detected, on the basis of the first period.

A PAM4 signal processor calibrates slicing thresholds to reduce bit error rate in a PAM4 clock data recovery circuit by determining a first target value of a first slicing level. The PAM4 signal processor is configured to retrieve the first target value of the first slicing level and sweeps a first reference voltage down from the upper voltage threshold. The PAM4 signal processor is further configured to detect a first filtered output associated with the first reference voltage and determines whether the first filtered output is higher than a target value. Responsive to determining that the first filtered output is higher than the target value, the PAM4 signal processor stores the first reference voltage value.

A software rational resampler is located in an audio buffer path to correct clock differences between a sender and a receiver. Counters track the frames into an audio buffer from the sender and the frames removed from an audio buffer by the receiver. A change in the difference between the sender frame counter and the receiver frame counter is detected and used as a triggering event to initiate changing the parameters of the software rational resampler. The software rational resampler parameters may be saved so that if audio is received from the same source, the software rational resampler is configured on system startup.

A method includes: scheduling transmission of a first synchronization signal by a first node; and scheduling transmission of a second synchronization signal by a second node. The method also includes, after transmission of the first synchronization signal: receiving, from the first node, a first phase reference associated with the first synchronization signal; and receiving, from the second node, a first phase-of-arrival of the first synchronization signal at the second node. The method additionally includes, after transmission of the second synchronization signal: receiving, from the second node, a second phase reference associated with the second synchronization signal; and receiving, from the first node, a second phase-of-arrival of the second synchronization signal at the first node. The method further includes calculating a propagation delay between the first node and the second node based on the first phase reference, the second phase reference, the first phase-of-arrival, and the second phase-of-arrival.

Methods, apparatus, and systems to synchronize Ethernet signals are disclosed. An example apparatus includes slicer circuitry having an input coupled to interface circuitry and having an output, the slicer circuitry configured to receive an analog signal corresponding to a first Analog to Digital Converter (ADC) clock in a plurality of ADC clocks and operable to determine symbols based on the analog signal; logic circuitry to determine whether there is a symbol transition in the symbols; timing error detector circuitry to update an error value in response to the determination that there is a symbol transition; timing loop circuitry to determine a frequency of voltage oscillations based on at least the error value; and phase interpolator circuitry to change a plurality of phase parameters corresponding to the plurality of ADC clocks at a rate given by the frequency of voltage oscillations.

A clock frequency divider circuit and a receiver are provided. The clock frequency divider circuit includes a reset retimer circuit configured to receive a reset signal and a clock signal, output a reset buffer signal of a differential signal pair obtained by buffering the reset signal, and output a reset synchronization signal obtained by synchronizing the reset signal with the clock signal, a clock buffer circuit configured to receive the clock signal and the reset synchronization signal and output a clock buffer signal of a differential signal pair obtained by buffering the clock signal, and an IQ divider circuit configured to output first through fourth output signals having different phases based on the reset buffer signal and the clock buffer signal.