A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.

A system is provided for synchronizing clocks. The system includes a plurality of devices in a network, each device having a local clock. The system is configured to synchronize the local clocks according to a primary spanning tree, where the primary spanning tree has a plurality of nodes connected through a plurality of primary links, each node of the plurality of nodes representing a respective device of the plurality of devices. The system is also configured to compute a backup spanning tree before a failure is detected in the primary spanning tree, wherein the backup spanning tree includes one or more backup links that are different from the primary links. As such, upon detection of a failure in the primary spanning tree, the system reconfigures the plurality of devices such that clock synchronization is performed according to the backup spanning tree.

A system is provided for synchronizing clocks. The system includes a plurality of devices in a network, each device having a local clock. The system is configured to synchronize the local clocks according to a primary spanning tree, where the primary spanning tree has a plurality of nodes connected through a plurality of primary links, each node of the plurality of nodes representing a respective device of the plurality of devices. The system is also configured to compute a backup spanning tree before a failure is detected in the primary spanning tree, wherein the backup spanning tree includes one or more backup links that are different from the primary links. As such, upon detection of a failure in the primary spanning tree, the system reconfigures the plurality of devices such that clock synchronization is performed according to the backup spanning tree.

A time-synchronization system according to the present disclosure includes a relay apparatus (10) configured to perform time-synchronization with a master apparatus (30) through a transmission system of which a transmission delay changes depending on a transmission direction, and a relay apparatus (20) configured to perform time-synchronization with the relay apparatus (10), in which the relay apparatus (20) transmits information about a difference between first time information obtained by performing time-synchronization with the relay apparatus (10) and second time information obtained from a time-synchronization source to the relay apparatus (10), and the relay apparatus (10) corrects third time information obtained by performing time-synchronization with the master apparatus (30) by using the information about the difference, and performs time-synchronization with a slave apparatus (50) by using the corrected third time information.

A system includes a first device, coupled to a link, which transmits a signal having a repeating pattern on one or more paths of the link. The system includes a second device coupled to the link and including one or more circuits and a time-to-digital converter (TDC). The second device is to receive at the one or more circuits the signal. The second device is to determine, by the TDC, a current duty cycle of the signal, the current duty cycle having a first duration associated with a first portion of the signal and a second duration associated with a second portion of the signal. The second device is further to determine the current duty cycle fails to satisfy a condition associated with a target duty cycle in response to determining the current duty cycle of the signal and adjust the current duty cycle to obtain an adjusted duty cycle.

A physical layer (PHY) processor of a network device receives: a timing packet that includes initial timing information, and one or more indicators of one or more parameters to be used by the PHY processor for embedding timing information into the timing packet, the one or more indicators including at least i) an indicator indicating that the timing packet is a type of packet into which timing information is to be embedded by the PHY device, ii) an indicator of a location of a field in the timing packet at which the timing information is to be embedded into the timing packet by the PHY device, and iii) an indicator of whether timing information in the timing packet needs to be updated by the PHY device. The PHY processor updates, based on the one or more indicators, the initial timing information in the timing packet.

A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.

There is provided a clock and data recovery circuit for a high-speed PAM-4 receiver through statistical learning. A clock and data recovery device according to an embodiment includes: an input unit through which data is inputted; a clock input unit through which a clock is inputted; a sampling unit configured to sample the inputted data by using the inputted clock; a controller configured to combine results of sampling at a plurality of sampling points, to determine a state of the clock based on the combined results, and to generate a control value for controlling the clock; and an adjustment unit configured to adjust the clock applied to the sampling unit, based on the control value generated by the controller. Accordingly, a hardware structure is simplified and energy efficiency is enhanced compared to an exiting oversampling clock and data recovery circuit for a PAM-4 receiver.

A clock frequency divider circuit and a receiver are provided. The clock frequency divider circuit includes a reset retimer circuit configured to receive a reset signal and a clock signal, output a reset buffer signal of a differential signal pair obtained by buffering the reset signal, and output a reset synchronization signal obtained by synchronizing the reset signal with the clock signal, a clock buffer circuit configured to receive the clock signal and the reset synchronization signal and output a clock buffer signal of a differential signal pair obtained by buffering the clock signal, and an IQ divider circuit configured to output first through fourth output signals having different phases based on the reset buffer signal and the clock buffer signal.