Provided is a synchronization signal block (SSB) transmission method performed by a communication device in a wireless communication system. The method is characterized in that: a time duration of a fixed frame period (FFP) is set for another communication device; and the SSB is periodically transmitted to the other communication device, wherein the SSB is periodically transmitted on each Nth FFP, said N being an integer greater than or equal to 1, and the transmission start time of the SSB is the first time resource included in each Nth FFP.

An input signal arranged in frames is received. The frames include a cyclic redundancy check (CRC) field including a number of bits having bit edges. A timing signal is generated to include adjustable duration waveforms at one of a first duration value and a second duration value. A CRC check determines the occurrence, over the duration, of a number of waveforms of the timing signal having their duration adjusted to one of the first duration value and the second duration value which corresponds to the number of bits. A check signal is produced having a pass/fail value. If pass, the duration of the waveforms in the timing signal is maintained adjusted to the one of the first duration value and the second duration value. If fail, the duration of the waveforms in the timing signal is re-adjusted to the other of the first duration value and the second duration value.

The method relates to a synchronization of a magnetic locating system including a first device and a second device each including an oscillator, a time counter clocked by the oscillator, and a radiocommunication module. The locating system also includes a device for emitting and receiving alternating magnetic fields, the device being configured to allow a propagation of alternating magnetic fields between the first and second devices, the device for emitting and receiving alternating magnetic fields being connected to the oscillators of the first and second devices. The synchronizing method includes a synchronizing step that is configured to synchronize the oscillators of the first and second devices by adjusting, by servo-controlling the oscillator of the second device, the operation of the time counter of the second device to the operation of the time counter of the first device.

Systems and methods are provided for master media clock recovery. In various embodiments, recovering a master media clock may comprise receiving clock reference format (CRF) packets carrying timestamps (Ts). Differences of Ts between adjacent CRF packets may be calculated, and an average difference of Ts between adjacent timestamps may be calculated. A recovered frequency of a master clock may be based on the calculated average difference of Ts between adjacent timestamps. The recovered frequency may be used to regulate a timing of, for example, a kernel module and/or a media application.

A PAM4 signal processor calibrates slicing thresholds to reduce bit error rate in a PAM4 clock data recovery circuit by determining a first target value of a first slicing level. The PAM4 signal processor is configured to retrieve the first target value of the first slicing level and sweeps a first reference voltage down from the upper voltage threshold. The PAM4 signal processor is further configured to detect a first filtered output associated with the first reference voltage and determines whether the first filtered output is higher than a target value. Responsive to determining that the first filtered output is higher than the target value, the PAM4 signal processor stores the first reference voltage value

A method comprising: accessing a response mapping defining a set of safety-critical functions associated with a safety-critical latency threshold and a set of safety responses, each safety response corresponding to a safety-critical function; executing a time-synchronization protocol with a transmitting system to calculate a clock reference; accessing a safety message schedule indicating an expected arrival time for each safety message in a series of safety messages based on the clock reference; for each safety message in the series of safety messages, calculating a latency of the safety message based on an arrival time of the safety message and the expected arrival time; and in response to a latency of a current safety message in the series of safety messages exceeding the safety-critical latency threshold, initiating the safety response corresponding to the safety-critical function for each safety-critical function in the set of safety-critical functions.

A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2.sup.N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.

In a method for establishing a communication link between a first network interface device and a second network interface device comprises, the second network interface device receives a training signal transmitted by the first network interface device. The training signal is for timing synchronization between the second network interface device and the first network interface device. The second network interface device determines, based on at least one physical characteristic of the training signal, a physical layer (PHY) parameter of the first network interface device. A controller of the second network interface device configures one or more components of the second network interface device to operate in a mode that corresponds to the determined PHY operating parameter of the first network interface device.

Systems and methods for providing input and output ports to connect to channels are provided. Input and output ports are the basic building blocks to create more complex data routing IP blocks. By aggregating these modular ports in different ways, different implementations of crossbar or Network on Chip (NoC) can be implemented, allowing flexible routing structure while maintaining all the benefits of channels such as robustness against delay variation, data compression and simplified timing assumptions.