Patent classifications
H04L7/0016
Synchronization between devices for PWM waveforms
A system includes a first controller configured to transmit a synchronization signal to a second controller. The second controller is configured to produce a PWM signal. The system also includes a counter configured to provide a count for the second controller, where the second controller is configured to initiate rising edges and falling edges of the PWM signal based on the count from the counter. The second controller is also configured to measure an error between a time when the synchronization signal is received at the second controller and an expected time of receipt for the synchronization signal. The second controller is also configured to adjust a period of the counter based at least in part on the error.
Hybrid serial receiver circuit
A hybrid receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. Depending on a baud rate of the serial data stream, either the digital receive circuit or the analog receiver circuit is activated to provide the desired performance and power consumption over the range of possible baud rates. The ADC-based receiver circuit may include multiple analog-to-digital converter circuits with different resolutions that can be selected for different baud rates.
Method of routing synchronization messages
A method of routing synchronization messages in a packet communication network, in which a packet is routed using a global routing table. A piece of equipment in the network implements the following steps: detecting a packet carrying a synchronization message in a packet stream; determining an output port; emitting a packet carrying the message at the determined output port, the message being modified using a piece of information representing a time of transit in the equipment. A synchronization routing table, which stores at least one association between an input port and at least one output port, is configured in the equipment. When the packet carrying the received message indicates a routing needs to be carried out using the synchronization table, the output port for this packet is determined by the equipment according to an input port on which the packet is received and by reading the synchronization table.
Multi-rate clock buffer
A system may include a driver circuit configured to receive a clock signal. The system may also include a first tuned circuit and a second tuned circuit. The first tuned circuit and the driver circuit may be collectively tuned according to a first frequency range. The first tuned circuit may be configured to be active when a rate of the clock signal is within the first frequency range and to be inactive when the rate is outside of the first frequency range. Further, the second tuned circuit and the driver circuit may be collectively tuned according to a second frequency range that is different from the first frequency range. The second tuned circuit may be configured to be active when the rate is within the second frequency range and to be inactive when the rate is outside of the second frequency range.
PREDICTING CLOCK DRIFTING
Disclosed is a method comprising obtaining a plurality of previous clock skews, a reported temperature and a reported time, based on the plurality of previous clock skews, the reported temperature and the reported time, obtaining a prediction of the current clock skew, determining a current clock offset based on the predicted current clock skew, determining a clock adjustment based on the current clock offset and the reported time, and determining a corrected time based on the clock adjustment.
Dynamic digital communication system control
Control of a digital communication system having a plurality of communication lines on which signals are transmitted and received is implemented using a variety of methods and systems. According to one embodiment of the present invention, a method is implemented where the signals are affected by interference during transmission and each of the communication lines has at least one transmitter and at least one receiver. A model is created of the interference characteristics due to the signals carried on the communication lines. Interference characteristics for a line are determined based on the model and actual signals carried on other communication lines different from the line for which the characteristics are being determined. Actual interference is compensated for on the communication line using the determined interference characteristics.
METHODS AND SYSTEMS FOR CALIBRATING CLOCK SKEW IN A RECEIVER
Methods and systems for calibrating clock skew in a SerDes receiver. A method includes detecting a skew in a clock with respect to an edge of a reference clock, based on a value sampled by the clock and a value sampled by the reference clock at an edge of a data pattern, for a first Phase Interpolator (PI) code; determining a count of the skew from a de-serialized data word including outcome values obtained based on values sampled by the clock and values sampled by the reference clock at a predefined number of edges of the data pattern; obtaining a skew calibration code corresponding to the first PI code, from a binary variable obtained by accumulating an encoded variable to a previously generated binary variable; and calibrating the skew by performing a positive phase shift or a negative phase shift to the clock based on the skew calibration code.
Precise time management using local time base
A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.
OPTIMIZED SECONDARY SYNCHRONIZATION SIGNAL
Methods, systems, and devices for wireless communication are described. A wireless communications system operating in millimeter wave (mmW) spectrum may utilize synchronization signals for beam tracking. A synchronization signal (e.g., primary synchronization signals (PSS), secondary synchronization signals (SSS), etc.), beam reference signal, and/or control signal may be designed to facilitate beam tracking. A synchronization signal structure based on a repeated sequence in the time domain may facilitate searching for different beams in a timely manner. In some cases, the repeated synchronization signal structure may be achieved by using a larger tone spacing, and hence having shorter symbol duration and repeating the short symbols in the time domain. The repeated structure may be further used to encode additional information (e.g., facilitated by the resulting additional degrees of freedom). Additionally or alternatively, a synchronization signal (e.g., SSS) may be discrete Fourier transform (DFT) pre-coded to achieve better peak-to-average-power-ratio (PAPR).
METHOD FOR ESTIMATING SYMBOLS CONVEYED BY A SIGNAL COMPRISING A PLURALITY OF CHIRPS, AND CORRESPONDING COMPUTER PROGRAM PRODUCT AND DEVICE
A method for estimating information symbols conveyed by a signal including modulated chirps. The modulation corresponds to circular permutation of the pattern of variation in the instantaneous frequency of a basic chirp over the symbol time. A first demodulation of a portion of the signal that is representative of at least two chirps delivering: an estimation of a first modulation symbol associated with a first chirp with a stronger amplitude among the two chirps, an estimation of the amplitude and phase of the first chirp, a generation of a signal that is representative of the first chirp from the estimation, and a coherent subtraction of the signal that is representative of the first chirp from the portion of the signal delivering an updated portion of the signal. A second demodulation of the updated portion delivering an estimation of a second modulation symbol associated with a second chirp.