A physical layer (PHY) processor of a network device receives: a timing packet that includes initial timing information, and one or more indicators of one or more parameters to be used by the PHY processor for embedding timing information into the timing packet, the one or more indicators including at least i) an indicator indicating that the timing packet is a type of packet into which timing information is to be embedded by the PHY device, ii) an indicator of a location of a field in the timing packet at which the timing information is to be embedded into the timing packet by the PHY device, and iii) an indicator of whether timing information in the timing packet needs to be updated by the PHY device. The PHY processor updates, based on the one or more indicators, the initial timing information in the timing packet.

A synchronization apparatus capable of reducing the effect of the fluctuations in synchronization signals that are caused when the synchronization signals are received through a network are provided. A synchronization apparatus (20) according to the present invention receives a synchronization signal transmitted from a synchronization signal source (10) through a network. The synchronization apparatus (20) includes a frequency synchronization unit (21) that performs frequency synchronization based on a received synchronization signal, and outputs a frequency synchronization signal, a phase synchronization unit (23) that performs phase synchronization based on a synchronization signal transmitted from the synchronization signal source (10) through a network, and outputs a phase synchronization signal, and a phase synchronization control unit (22) that generates an offset value by using a phase difference between the frequency synchronization signal and the phase synchronization signal, and corrects a phase of the frequency synchronization signal by using the offset value.

A system and module for, and a method of correcting, memory misalignment in a phase shift keying receiver is disclosed. Embodiments include a system having: an analog front end for receiving a demodulated signal having a preamble portion, and for generating a digital register input signal including a received preamble portion; a finite state machine for selecting a memory address of the demodulated signal based on the received preamble portion; a preamble memory for storing all possible preambles contained within the demodulated signal and for supplying a selected preamble memory output corresponding to the selected memory address; and a memory alignment module configured to compare phase information of symbols of the preamble portion and preamble phase information of symbols of the selected preamble memory output. This system checks that the preamble portion of the register input signal aligns with the selected preamble memory output and makes corrections when necessary.

The Direct Synthesis of a Receiver Clock (DSRC) contributes a method, system and apparatus for reliable and inexpensive synthesis of inherently stable local clock synchronized to a referencing signal received from an external source. Such local clock can be synchronized to a referencing frame or a data signal received from wireless or wired communication link and can be utilized for synchronizing local data transmitter or data receiver. Such DSRC can be particularly useful in OFDM systems such as LTE/WiMAX/WiFI or Powerline/ADSL/VDSL, since it can secure lower power consumption, better noise immunity and much more reliable and faster receiver tuning than those enabled by conventional solutions.

A system includes a first controller configured to transmit a synchronization signal to a second controller. The second controller is configured to produce a PWM signal. The system also includes a counter configured to provide a count for the second controller, where the second controller is configured to initiate rising edges and falling edges of the PWM signal based on the count from the counter. The second controller is also configured to measure an error between a time when the synchronization signal is received at the second controller and an expected time of receipt for the synchronization signal. The second controller is also configured to adjust a period of the counter based at least in part on the error.

A node synchronization method, includes: receiving a synchronization message by a first synchronization node in a network; determining whether to update a first local time of the first synchronization node according to the synchronization message by the first synchronization node; updating the first local time according to a synchronization time of the synchronization message by the first synchronization node when determining to update the first local time; and updating the synchronization time of the received synchronization message with the current first local time and forwarding the updated synchronization message by the first synchronization node.

Disclosed embodiments relate, generally, to improved data reception handling at a physical layer (PHY). Some embodiments relate to end of line systems that include legacy media access control (MAC) and PHY that implement improved data reception handling disclosed herein. The improved data reception handling improves the operation of the end of line systems, and the MAC more specifically, and in some cases to comply with media access tuning protocols implemented at the physical layer.

A data reception device includes: an equalizer circuit that shapes a waveform of an input signal according to a set gain value; a CDR circuit which recovers a plurality of clock signals having different phases in one cycle from the input signal after being subjected to the waveform shaping performed by the equalizer circuit; an oversampler which performs sampling of the waveform-shaped input signal in synchronization with the plurality of clock signals and recovers a plurality of input data from the waveform-shaped input signal; and a calibration control unit which determines whether the oversampler correctly recovers the input data based on a result of the sampling performed by the oversampler, and generates a control signal to set the gain value of the equalizer circuit based on a determination result when it is determined that the input data is not correctly recovered.

A translation device, a test system, and a memory system are provided. The translation device includes plural first input/output (I/O) circuits that respectively transmit and receive first signals through plural pins based on a pulse amplitude modulation (PAM)-M mode, a second I/O circuit that transmits and receives a second signal through one or more pins based on a PAM-N mode, and a translation circuit that translates the first signals into the second signal and translates the second signal into the first signals. M and N are different integers of 2 or more.

According to one aspect of the teachings herein, a method and apparatus predict a departure time of transmit data transmitted from a first network entity to a second network entity, determine a timing difference between a detected departure time and the predicted departure time of the transmit data that is was based on an estimated path delay of data transmission circuitry, and indicate the timing difference in further transmit data, e.g., to improve synchronization at the second network entity. In one or more embodiments, the timing difference is further used to compensate one or more timing operations at the first network entity, such as adapting one or more prediction parameters used by a departure-time prediction process.