A testing system includes a signal generator circuit, a jitter modulation circuit, and an oscilloscope circuit. The signal generator circuit is configured to generate a clock pattern signal with a single clock pattern frequency. The jitter modulation circuit is configured to generate a jitter signal. A device-under-test is configured to receive an input signal. The input signal is a combination signal of the clock pattern signal and the jitter signal. The device-under-test includes a clock data recovery circuit and is further configured to generate an output signal according to the input signal. The oscilloscope circuit is configured to receive the output signal for determining performance of the clock data recovery circuit.

There is disclosed a synchronous digital circuit having a system clock and for processing a data signal, wherein the digital circuit comprises a data path, a hard macro having a macro input, a logic circuit in the data path upstream of the macro input and having a first part and a second part, the second part being immediately upstream of the macro input, a set-up timing error detector having an input, wherein the input is on the data path between the first part and the second part, and a timing correction unit, wherein the data transit time across the second part is equal to or less than one half of a clock period, and wherein the timing correction unit is configured to correct, in response to the set-up timing error detector detecting a set-up timing error, the detected set-up timing error before the data reaches the macro input.

Technology for an eNodeB operable to configure measurement subframes for a user equipment (UE) is disclosed. The eNodeB can identify a first set of orthogonal frequency division multiplexing (OFDM) symbols of a measurement subframe to transmit a plurality of primary synchronization signals (PSS) to the UE in the measurement subframe. The eNodeB can identify a second set of OFDM symbols of the measurement subframe to transmit a plurality of secondary synchronization signals (SSS) to the UE in the measurement subframe. The eNodeB can encode the plurality of primary synchronization signals (PSS) for transmission to the UE using the first set of OFDM symbols of the measurement subframe. The eNodeB can encode the plurality of secondary synchronization signals (SSS) for transmission to the UE using the second set of OFDM symbols of the measurement subframe.

A network system includes at least one node configured to exchange messages through a set of communication links. Each node includes a synchronizer, a set of monitors in communication with the synchronizer, a physical oscillator and a state timer clock and a local timer clock, each clock being driven by the physical oscillator and having a variable clock value that locally tracks passage of clock time for the node. The network system is configured to execute a synchronization process when a specified condition occurs. Upon receiving a Sync message, each of the nodes is configured to store an incoming Sync message, increment a local timer clock value, or ignore the Sync message based on a local timer clock value associated with an incoming Sync message.

A FlexRay network guardian including: a resetting leading coldstart node (RLCN) detector configured to detect a RLCN failure; a deaf coldstart node (DCN) detector configured to detect a DCN failure; a babbling idiot (BI) detector configured to detect a BI failure; and a FlexRay network decoder configured to output a signal regarding the status of the FlexRay network to the RLCN detector, DCN detector, and BI detector, wherein the RLCN detector, DCN detector, and BI detector are configured to send an indication of a failure to a containment module.

Disclosed embodiments relate to a system that changes transmitter and/or receiver settings to deal with reliability issues caused by a predetermined event, such as a change in a power state or a clock start event. One embodiment uses a first setting while operating a transmitter during a normal operating mode, and a second setting while operating the transmitter during a transient period following the predetermined event. A second embodiment uses similar first and second settings in a receiver, or in both a transmitter and a receiver employed on one side of a bidirectional link. The first and second settings can be associated with different swing voltages, edge rates, equalizations and/or impedances.

System and method of frame alignment at a receiver with power optimization mechanisms. A framer is configured to perform a frame alignment process on a data stream and enter an inactive state after frame alignment is achieved. In the inactive state, the circuits used to perform the frame alignment process in the framer can be powered down or otherwise placed in a power reduction mode. Responsive to an indication that data processing at the receiver becomes out-of-frame again, the framer can wake up from the inactive state and restart the frame alignment process. An out-of-frame indication may be generated by error detection logic (e.g., forward error correction (FEC) decoder) when it detects an excessive number of uncorrectable errors.

System and method of frame alignment at a receiver with power optimization mechanisms. A framer uses one or more comparators to search for the FAW in the incoming data, with each comparator configured to serially compare multiple windows of a parallel M-bit block (as provided from a parallel data bus) with the FAW. Multiple comparators in the framer may operate in parallel to search for the FAW at different windows. This configuration can significantly reduce the comparator count and so the gate count as well as the chip area in a framer. Power consumption can be advantageously reduced as one comparator operating serially consumes less power than multiple comparators in parallel because less gate toggling is involved.

According to an embodiment, a communication device includes a phase-shifting circuit that shifts a phase of a local signal and supplies it to an orthogonal demodulator. The phase-shifting circuit includes first and second signal input ends that are supplied with an output signal of a local oscillator between both ends thereof, a frequency divider that has first and second input ends, and a switching part that is provided between the first and second signal input ends and the first and second input ends of the frequency divider and switches connection between the first and second signal input ends and the first and second input ends of the frequency divider.

A robust frequency drift tracking receiver. The received signal is translated to an intermediate frequency in the RF stage by a quadrature demodulator, and is then brought into the base band by a digital mixer made by a CORDIC. A base band processing stage allows for a synchronization of the receiver relative to the data frame, to estimate data and to output a counter-reaction signal to the CORDIC, obtained by integration of successive frequency corrections, with a predetermined step.