Time of day (ToD) registers provide respective virtual ToDs corresponding to the occurrence of edges of input clock signals being supplied to an integrated circuit. The integrated circuit generates a heartbeat clock signal having a frequency higher than a SYNC signal and time stamps the heartbeat clock signal to generate heartbeat time stamps. The heartbeat time stamps are used along with the time stamps of the input clock signals to determine the time of day corresponding to occurrences of edges of the input clock signals.

In some aspects, the disclosure is directed to methods and systems for synchronized multi-client content delivery, and a content selection system based on individual and aggregated scores for the content items, to generate bundles or sets of content items having approximately corresponding scores. Server timers and local timers on client devices may be synchronized via notifications, and timer durations dynamically adjusted when client requests and responses are sent prior to client-side timer expiration, but received after server-side timer expiration, indicating communication latency has caused desynchronization. Timers may be adjusted on a global basis or per-client device basis. Through scoring and bundling, sets of content items that may be relevant to approximately an equal share of the recipient client devices may be selected and transmitted.

A network element, for use in an automotive network in a vehicle, includes one or more ports, packet processing circuitry and a validation data collector. The one or more ports are configured for communicating over the automotive network in the vehicle. The packet processing circuitry is configured to receive packets from the automotive network via the one or more ports, the packets including time-protocol packets, to process the received packets, and to forward the processed packets to the automotive network via the one or more ports. The validation data collector is configured to derive, from at least some of the time-protocol packets that are processed by the packet-processing circuitry, validation data indicative of compliance of the network element with a vehicle-safety requirement, and to make the validation data accessible from outside the network element.

An automotive network system in a vehicle includes one or more non-compliant network switches, one or more validation data collectors, and a safety validator. The non-compliant network switches are installed in the vehicle but are not compliant with specified vehicle-safety requirements. The non-compliant network switches are configured to receive, process and send packets. The validation data collectors are coupled to the non-compliant network switches and are configured to derive validation data from at least some of the packets traversing the network switches. The safety validator is configured to verify whether the non-compliant network switches function in a manner that in actuality is compliant with the vehicle-safety requirements based on the validation data collected by the one or more validation data collectors.

A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

A method and apparatus for clock recovery is provided. The method begins when a reference pulse is extracted from a signal. This reference pulse is then compared with a clock signal. A phase of the extracted reference signal is then detected, and is done in relation to the clock signal. Phase differences between the extracted reference signal with respect to the clock signal are accumulated over a predetermined period of time. This accumulating continues until a predetermined number of phase differences has been accumulated. The accumulated phase differences are then averaged. The apparatus includes: a phase detector; a phase averaging unit in communication with a clock generator and a controller; a lock detector in communication with the phase averaging unit and a loop filter; at least one adder; at least one bypass filter; and at least one accumulator.

Systems and methods for high speed communications are described herein. In certain aspects, the systems and methods include innovative transceiver architectures and techniques for re-timing, multiplexing, de-multiplexing and transmitting data. The systems and methods can be used to achieve reliable high-speed point-to-point communication between different electronic devices, computing devices, storage devices and peripheral devices.

Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

A method for processing a digital audio broadcast signal in a radio receiver includes: receiving a digital audio broadcast signal; demodulating the digital audio broadcast signal to produce an analog audio stream and a digital audio stream; determining a digital signal quality value for the digital audio stream; blending an output of the radio receiver from the analog audio stream to the digital audio stream when the digital signal quality value exceeds an adaptive analog-to-digital threshold value; and blending the output of the radio receiver from the digital audio stream to the analog audio stream when the digital signal quality value falls below an adaptive digital-to-analog threshold value, wherein the adaptive digital-to-analog threshold value is lower than the adaptive analog-to-digital threshold value.

Methods and systems are provided for guard band detection and/or frequency offset detection. For example, a signal processing circuit may be operable to determine, for each of a plurality of downconverted signals, one or more frequency offsets that are associated with one or more corresponding local oscillators (LOs) used in obtaining the plurality of downconverted signals; and relating to the determined frequency offsets may be generated for the plurality of downconverted signals. The signal processing circuit may perform, based on the generated information, one or both of a band stacking operation and a channel stacking operation so as to prevent channels/bands being stacked on each other or being overlapped.