A wireless station includes at least one oscillator to output a reference signal, and an error calculator to calculate a frequency of the reference signal and calculate a frequency error by subtracting a target frequency of the reference signal from the calculated frequency of the reference signal. The wireless station further includes a modulation data generator to generate modulation data by adding a correction value, varying in negative correlation with the frequency error calculated by the error calculator, to data to be transmitted, and a modulator to conduct frequency modulation on the basis of the modulation data and the reference signal.

The present disclosure relates to a communication device, a communication method, and a program that make it possible to perform an appropriate output control based on time synchronization for a plurality of sensors. There are provided: a communication processing control section that controls communication processing in accordance with a predetermined standard with a plurality of sensors; and a time synchronization counter to implement a timing control defined in the standard. Then, information processing is performed that is necessary for an output control that causes the time synchronization counter to time synchronize with time synchronization counters included in the respective sensors to output time data indicating a timing at which sampling data is sampled together with the sampling data sampled at a predetermined sampling cycle in the plurality of sensors. The present technology is applicable, for example, to a communication system employed in a movable body including the plurality of sensors.

A multi-lane transmitting apparatus includes lanes, and each lane includes a serializer circuit to convert parallel bits to serial bits. A clock signal generator generates a first clock signal having phases. A deserializer circuit converts serial bits to parallel bits. A Built-In Self-Test (BIST) circuit includes a signal generator circuit for generating a signal having bits in a defined pattern. A comparator circuit compares a pattern of bits of an output signal with the defined pattern. A BIST lane circuit monitors a status of the lanes. A BIST central circuit receives the status and determines if a number of lanes having an unmatched status is less than a threshold value. A phase extrapolator circuit adjusts a phase of the first clock signal when the number of the lanes is less than the threshold value.

A multi-lane transmitting apparatus includes lanes, and each lane includes a serializer circuit to convert parallel bits to serial bits. A clock signal generator generates a first clock signal having phases. A deserializer circuit converts serial bits to parallel bits. A Built-In Self-Test (BIST) circuit includes a signal generator circuit for generating a signal having bits in a defined pattern. A comparator circuit compares a pattern of bits of an output signal with the defined pattern. A BIST lane circuit monitors a status of the lanes. A BIST central circuit receives the status and determines if a number of lanes having an unmatched status is less than a threshold value. A phase extrapolator circuit adjusts a phase of the first clock signal when the number of the lanes is less than the threshold value.

Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.

A method and system for the post-adjustment (i.e., offline) of event timestamps to implement virtual time synchronization amongst detection node clocks. In existing methodologies with the goal of clock synchronization, clocks (and timestamps generated therefrom) are disciplined or adjusted at the recordation time of the events on a detection node (e.g., a switch/router, an Internet-of-Things (IoT) device, a wireless sensor, etc.). However, there is no particular reason for these clocks or timestamps to be accurate during the recordation time, but rather, should be accurate at their use or interpretation time. Further, through these recordation time adjustments, clock drifts and timing errors may be gradually introduced, leading to runaway inaccuracies. The disclosed method and system intentionally avoids the disciplining of clocks at event recordation times on the detection node and, instead, adjusts timestamps during interpretation times, to overcome the aforementioned issues.

Systems and methods are disclosed for adjusting Radio Link Monitoring (RLM), Radio Link Failure (RLF) detection, RLF recovery, and/or connection establishment failure detection for wireless devices (16) in a cellular communications network (10) depending on mode of operation. In one embodiment, a node (14, 16) in the cellular communications network (10) determines whether a wireless device (16) (e.g., a Machine Type Communication (MTC) device) is to operate in a long range extension mode of operation or a normal mode of operation. The node (14, 16) then applies different values for at least one parameter depending on whether the wireless device (16) is to operate in the long range extension mode or the normal mode. The at least one parameter includes one or more RLM parameters, one or more RLF detection parameters, and/or one or more RLF recovery parameters. In doing so, signaling overhead and energy consumption within the wireless device (16) when operating in the long range extension mode is substantially reduced.

The present invention relates to the field of digital signal processing, and in particular to a Costas sequence time-frequency joint synchronization method based on all-phase spectrum correction. The method improves the defects existing in a discrete frequency spectrum correction algorithm using short-time Fourier transform and sliding correlation. The improvement mainly comprises: the present disclosure provides a solution based on iterative optimization: when an actual frequency offset is an integral multiple of the spectral resolution, a large error can occur, frequency offset correction and time delay correction are carried out on a signal by using an estimated value having a large estimated error, then estimation is carried out again, and the frequency offset of the signal is not a special value by means of an iteration mode.

A semiconductor integrated circuit for a radio communication terminal sequentially uses a plurality of frequency channels by instructions from a hopping frequency decision unit to receive packet data by a reception unit. When the integrated circuit cannot detect the head of the packet data in reception operations, the integrated circuit cannot receive packet data should be received originally then assumes that the received packet data is a packet error. And the integrated circuit calculates packet error rates for each frequency channel on the basis of the number of times of reception operations performed for each frequency channel and of the number of times of packet errors to estimate channel qualities by using the packet error rates.

A signal processing method includes receiving a digital signal including a sequence of samples. For each sample among at least some of the samples, a neighbor-based estimate is calculated over (i) one or more samples that precede the sample in the sequence and (ii) one or more samples that succeed the sample in the sequence, and an error value, indicative of a deviation of the neighbor-based estimate from an actual value of the sample, is calculating. An impairment in the digital signal is estimated based on a plurality of error values calculated for a plurality of the samples.