A testing system includes a signal generator circuit, a jitter modulation circuit, and an oscilloscope circuit. The signal generator circuit is configured to generate a clock pattern signal with a single clock pattern frequency. The jitter modulation circuit is configured to generate a jitter signal. A device-under-test is configured to receive an input signal. The input signal is a combination signal of the clock pattern signal and the jitter signal. The device-under-test includes a clock data recovery circuit and is further configured to generate an output signal according to the input signal. The oscilloscope circuit is configured to receive the output signal for determining performance of the clock data recovery circuit.

Provided is a method for calculating a timestamp associated with a data packet before transcoding of the data packet. The method may include sampling a time of day (TOD) signal to provide a sampled TOD. A previously sampled TOD estimate may be retrieved. An internal TOD estimate may be determined based on the sampled TOD and the previously sampled TOD estimate. A timestamp may be determined based on the internal TOD estimate. A system and computer program product are also disclosed.

In one embodiment, a processing apparatus includes processing circuitry to process an event, a timestamping unit to generate a timestamp for the event, at least one register to store at least one parameter describing a hardware state of the processing circuitry, and timestamp correction processing circuitry to compute a time value as a correction to the generated timestamp responsively to the at least one parameter.

Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.

A time-synchronization system according to the present disclosure includes a relay apparatus (10) configured to perform time-synchronization with a master apparatus (30) through a transmission system of which a transmission delay changes depending on a transmission direction, and a relay apparatus (20) configured to perform time-synchronization with the relay apparatus (10), in which the relay apparatus (20) transmits information about a difference between first time information obtained by performing time-synchronization with the relay apparatus (10) and second time information obtained from a time-synchronization source to the relay apparatus (10), and the relay apparatus (10) corrects third time information obtained by performing time-synchronization with the master apparatus (30) by using the information about the difference, and performs time-synchronization with a slave apparatus (50) by using the corrected third time information.

In some aspects, the disclosure is directed to methods and systems for synchronized multi-client content delivery, and a content selection system based on individual and aggregated scores for the content items, to generate bundles or sets of content items having approximately corresponding scores. Server timers and local timers on client devices may be synchronized via notifications, and timer durations dynamically adjusted when client requests and responses are sent prior to client-side timer expiration, but received after server-side timer expiration, indicating communication latency has caused desynchronization. Timers may be adjusted on a global basis or per-client device basis. Through scoring and bundling, sets of content items that may be relevant to approximately an equal share of the recipient client devices may be selected and transmitted.

There is provided a clock and data recovery circuit for a high-speed PAM-4 receiver through statistical learning. A clock and data recovery device according to an embodiment includes: an input unit through which data is inputted; a clock input unit through which a clock is inputted; a sampling unit configured to sample the inputted data by using the inputted clock; a controller configured to combine results of sampling at a plurality of sampling points, to determine a state of the clock based on the combined results, and to generate a control value for controlling the clock; and an adjustment unit configured to adjust the clock applied to the sampling unit, based on the control value generated by the controller. Accordingly, a hardware structure is simplified and energy efficiency is enhanced compared to an exiting oversampling clock and data recovery circuit for a PAM-4 receiver.

Provided are a device synchronization method and apparatus, a device, and a storage medium. The device synchronization method includes: in response to determining that a second device does not receive a first data packet, determining a target time cycle for sending data packets by the second device based on a preset cycle adjustment parameter and a preset time slice length; determining whether the second device receives a second data packet sent by the first device based on the time slice length and the target time cycle of the second device; and in response to determining that the second device receives the second data packet sent by the first device, determining a time point for sending a data packet next time by the second device according to data packet information of the first device, achieving cycle synchronization of the second device in a preset synchronization cycle time period.

A clock data recovery circuit detects illegal decisions for received data, accumulates a phase gradient for the data, determines a number of the illegal decisions in a configured window for receiving the data, and if the number of the illegal decisions exceeds a pre-defend number in the window, applies a sum of the accumulated phase gradient and a phase increment having a sign of the accumulated phase gradient to a clock circuit for the data receiver.

Methods and systems are described for sequentially obtaining a plurality of data streams, the plurality of data streams comprising a data stream in a current condition, a data stream in a skewed-forward condition, and a data stream in a skewed-backward condition, calculating, for each data stream in the plurality of data streams, a corresponding set of cost-function values by obtaining a corresponding set of eye measurements, the eye measurements obtained by adjusting a sampling threshold of a sampler generating a plurality of samples of the data stream, the plurality of samples comprising edge samples and data samples, wherein the data stream is sampled at a rate equal to twice a rate of the data stream and calculating the corresponding set of cost-function values based on the corresponding set of eye measurements, and generating a skew control signal based on a comparison of the sets of calculated cost-function values.