Multiphase switched mode power supply clock apparatus, systems, articles of manufacture, and related methods are disclosed. An example apparatus includes a first clock recovery circuit to in response to obtaining a first clock pulse, transmit the first clock pulse to a power converter to cause the power converter to switch based on the first clock pulse, in response to obtaining a second clock pulse after the first clock pulse re-transmit the second clock pulse to a second clock recovery circuit, and increment a count value, and in response to the count value meeting a phase selection value, reset the count value.

A hybrid receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. Depending on a baud rate of the serial data stream, either the digital receive circuit or the analog receiver circuit is activated to provide the desired performance and power consumption over the range of possible baud rates. The ADC-based receiver circuit may include multiple analog-to-digital converter circuits with different resolutions that can be selected for different baud rates.

In some implementations, an optical receiver may receive, from an optical transmitter, a signal that is based on a clock of the optical transmitter. The optical receiver may generate a sampling clock signal that is swept over a range of sampling rates. The optical receiver may perform, using the sampling clock signal at a sampling rate of the range of sampling rates, oversampling of the signal to detect transition edges of the signal. The optical receiver may determine that the detected transition edges are indicative of a correspondence between the sampling rate and a data rate of the signal. The optical receiver may terminate sweeping of the sampling clock signal over the range of sampling rates based on the correspondence between the sampling rate and the data rate. The optical receiver may adjust the sampling clock signal to align the sampling clock signal with transition edges of the signal.

A clock recovery circuit comprises an input node receiving a data signal having a data rate, and a digital oscillator producing a local clock signal with a frequency higher than the data rate. A counter clocked by the local clock signal has its count value sampled and reset at the rising and falling edges of the data signal, and a storage block coupled to the counter stores a count value that is updated in response to the current sampled count value of the counter lying in an update range between lower and upper bounds. A threshold value set is produced as a function of the updated count value stored in the storage block. Sampling circuitry receives and samples the data signal, and provides a sampled version of the data signal in response to the count value of the counter reaching any of the threshold values.

Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.

A system for generating a self-receive signal includes: a signal generator; a first signal processor; a second signal processor; and an antenna. The system also includes a first passive coupling device: defining a first input port electromagnetically coupled to the signal generator; defining a first transmitted port; defining a first coupled port electromagnetically coupled to the first signal processor; and characterized by a first phase balance between the first transmitted port and the first coupled port. The system further includes a second passive coupling device: defining a second input port electromagnetically coupled to the antenna; defining a second transmitted port electromagnetically coupled to the first transmitted port; defining a second coupled port electromagnetically coupled to the second signal processor; and characterized by a second phase balance between the second transmitted port and the second coupled port substantially similar to the first phase balance.

A method for detecting a constant envelope burst-mode radio frequency (RF) signal with a known periodic synchronization sequence (PSS) represented therein includes transforming an incoming RF signal into a digital baseband signal (DBS), and processing the phase domain part by: 1) applying a correlation algorithm to correlate the DBS with a synchronization pattern corresponding to the PSS, 2) filtering the resulting correlation signal for removing at least a DC component of the correlation signal, 3) down-sampling the filtered correlation signal with a sampling time controlled by a clock aligned with amplitude peaks in the filtered correlation signal, 4) performing a decision algorithm on the down-sampled signal to determine if PSS is present in the incoming RF signal, then 5) generating an output signal indicating if the known PSS is present in the incoming RF signal, in response to a result of the decision algorithm.

In some aspects, the disclosure is directed to methods and systems for synchronized multi-client content delivery, and a content selection system based on individual and aggregated scores for the content items, to generate bundles or sets of content items having approximately corresponding scores. Server timers and local timers on client devices may be synchronized via notifications, and timer durations dynamically adjusted when client requests and responses are sent prior to client-side timer expiration, but received after server-side timer expiration, indicating communication latency has caused desynchronization. Timers may be adjusted on a global basis or per-client device basis. Through scoring and bundling, sets of content items that may be relevant to approximately an equal share of the recipient client devices may be selected and transmitted.

A network interface device operates in a normal transmit operating mode in which the network interface device continually receives transmission symbols from a link partner via the communication link. The network interface device determines that receive circuitry of the network interface device is to transition to a low power mode in response to receiving a sleep signal from the link partner. The network interface device then operates according to a quiet/refresh cycle of the low power mode to conserve power. The quiet/refresh cycle corresponds to a time schedule that includes a refresh time window in which receive circuitry of the network interface device is to be powered to receive a refresh signal from the link partner Immediately after transmission of the sleep signal, the network interface device transitions to a quiet time window of the time schedule in which the network interface device ignores transmissions from the link partner.

There is provided a clock and data recovery circuit for a high-speed PAM-4 receiver through statistical learning. A clock and data recovery device according to an embodiment includes: an input unit through which data is inputted; a clock input unit through which a clock is inputted; a sampling unit configured to sample the inputted data by using the inputted clock; a controller configured to combine results of sampling at a plurality of sampling points, to determine a state of the clock based on the combined results, and to generate a control value for controlling the clock; and an adjustment unit configured to adjust the clock applied to the sampling unit, based on the control value generated by the controller. Accordingly, a hardware structure is simplified and energy efficiency is enhanced compared to an exiting oversampling clock and data recovery circuit for a PAM-4 receiver.