A signal receiving device may include a high-speed receiving circuit, a low-speed receiving circuit, a low-speed synchronization circuit and a low-speed synchronization circuit. The high-speed receiving circuit receives an input signal and generate a high-speed received signal in a first operation mode. The high-speed synchronization circuit generates a high-speed synchronized signal to synchronize the high-speed received signal with a clock signal. The low-speed receiving circuit receives the input signal and generate a low-speed received signal in a second operation mode. The low-speed synchronization circuit generates a low-speed synchronized signal to synchronize the low-speed received signal with the clock signal. According to an operation mode, one of the high-speed synchronized signal and the low-speed synchronized signal is selected as an internal signal.

Method and system for managing the reception of data frames, scheduled statically and periodically, a frame includes a header provided with an identifier (id) of the frame and an index (index) representing the occurrence of the frame in a hyper-period.

A signal receiving device may not need to consider jitter characteristics of a received signal by including a transition detecting device which receives first to third input signals having different signal levels for each unit interval, compares whether a signal level of a first differential signal, which is a differential signal between the first input signal and the second input signal among the first to third input signals, is greater than a first reference signal level to output a first comparison signal, and compares whether the signal level of the first differential signal is greater than a second reference signal level different from the first reference signal level to output a second comparison signal, and a clock data recovering device which recovers a clock signal embedded in the first to third input signals on the basis of the first and second comparison signals to output the recovery clock signal.

A method for synchronizing networks is disclosed. A first wired communication system having a first time base is set up in a first network. A second wired communication system having a second time base is set up in a second network. The first network and the second network are connected to a wireless communication system via a first translation unit and a second translation unit, respectively. The first translation unit and the second translation unit are synchronized to one another according to a third time base of the wireless communication system independently of the first time base and the second time base. A third synchronization message is transmitted from the first translation unit to the second translation unit. A transmission time for the third synchronization message in the third time base is determined and is used to synchronize the second time base to the first time base.

A method and apparatus according to the present invention addresses and/or prevents lost protocol synchronization in HARQ systems caused by ACK/NACK errors. One embodiment detects lost synchronization errors for NDI-based retransmission protocols and restores synchronization by sending an explicit RESET message. In response to the RESET message, the transmitter aborts the transmission of a current PDU and transmits a new PDU and corresponding NDI. Another embodiment prevents protocol synchronization errors by sending scheduling grants on a packet by packet basis. The receiver sends a subsequent explicit scheduling grant to the transmitter based on an error evaluation of a received PDU. The transmitter will not send the next PDU unless it receives the subsequent explicit scheduling grant.

A circuit for performing clock recovery according to a received digital signal. The circuit includes at least an edge sampler and a data sampler for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock and data clock signals offset in phase from one another to the respective clock inputs of the edge sampler and the data sampler. A digital phase detector determines if the data clock is early, late or synchronized with respect to data value transitions in the digital signal, and based on that determination provides a phase adjustment signal to the clock signal supply circuit, which is operable to vary phases of the data and edge clock signals accordingly.

A method for processing a radio signal includes producing first and second streams of audio samples; decimating the first and second streams of audio samples to produce first and second streams of decimated streams of audio samples; estimating a first offset value between corresponding samples in the first and second streams of decimated streams of audio samples; shifting one of the first and second streams of audio samples by a first shift value; decimating the first and second streams of audio samples to produce third and fourth streams of decimated audio samples; estimating a second offset value; determining a final offset value based on an intersection of ranges of valid results of the first and second offset values; and shifting one of the first and second streams of audio samples by the final offset value to align the first and second streams of audio samples.

The present disclosure includes a time-to-digital converter (TDC) based RF-to-digital (RDC) data converter for time domain signal processing polar receivers. Polar data conversion achieves better SNR tolerance owing to its phase convergence near the origin in a polar coordinate. The proposed RDC consists of a TDC for phase detection and an analog-to-digital converter (ADC) for amplitude conversion. Unlike the conversional data converter, the proposed ADC's sampling position is guided by the detected phase result from the TDC's output. This TDC assisted data-converter architecture reduces the number of bits required for the ADC. In addition, oversampling is no longer needed. With precisely controlled tunable delay cells and gain compensator, this hybrid data convertor is capable to directly convert Quadrature Amplitude Modulation (QAM) waveforms and Amplitude Phase Shift Keying (APSK) waveforms directly from the RF signal without down-conversion. Thus, the proposed RDC architecture achieves lower power consumption and better performance comparing with conventional I/Q receivers.

Certain aspects of the present disclosure provide techniques for signaling information regarding beams used for data and control transmissions to a UE. For example, a method for wireless communications by a user equipment (UE), may generally include signaling information to a base station (BS) that the UE is seeking recovery of a beamformed link between the BS and the UE, and participating in recovery of the beamformed link in accordance with the information. A method for wireless communications by a base station (BS), may generally include receiving information from a user equipment (UE) that the UE is seeking recovery of a beamformed link between the BS and the UE, and participating in recovery of the beamformed link in accordance with the information.

A method of calibrating a clock phase and a voltage offset includes receiving an input data signal that is periodically toggled. A clock phase calibration operation is performed based on an up signal and a down signal, such that phases of a plurality of clock signals are adjusted. The up signal and the down signal are generated based on the input data signal, a reference voltage and the plurality of clock signals. A voltage offset calibration operation is performed based on the up signal, the down signal and a first sample data signal, such that a voltage level of the reference voltage is adjusted. The first sample data signal is generated by sampling the input data signal based on one of the plurality of clock signals. The clock phase calibration operation and the voltage offset calibration operation are performed independently of each other and not to overlap with each other.