There are provided examples of receivers, controller units and related methods, wherein one receiver includes: an adjustable sample provider configured to provide samples of an input signal using an adjustable sample timing; a feedback path configured to provide a feedback signal to the adjustable sample provider on the basis of a timing error, wherein the feedback path includes a loop filter configured to provide sample timing information to the adjustable sample provider; and a replacement value provider configured to provide a replacement sample timing information replacing the sample timing information provided by the feedback path when an input signal does not fulfil a predetermined requirement for a feedback-based sample timing adaptation, wherein the replacement value provider is configured to provide the replacement sample timing information considering a timing error information, or a quantity derived from the timing error information, over a longer time period when compared to a time period considered by the loop filter for a provision of the sample timing information.

A circuit for estimating a time difference between a first signal and a second signal includes a first signal line for receiving the first signal; a delay unit configured to receive the second signal and delay the second signal so as to provide a plurality of delayed versions of the second signal, each delayed version being delayed by a different amount of delay to the other delayed versions; a comparison unit configured to compare each of the delayed versions of the second signal with the first signal so as to identify which of the delayed versions of the second signal is the closest temporally matching signal to the first signal; and a difference estimator configured to estimate the time difference between the first and second signals in dependence on the identified delayed version.

There are provided examples of receivers, controller units and related methods, wherein one receiver includes: an adjustable sample provider configured to provide samples of an input signal using an adjustable sample timing; a feedback path configured to provide a feedback signal to the adjustable sample provider on the basis of a timing error, wherein the feedback path includes a loop filter configured to provide sample timing information to the adjustable sample provider; and a replacement value provider configured to provide a replacement sample timing information replacing the sample timing information provided by the feedback path when an input signal does not fulfil a predetermined requirement for a feedback-based sample timing adaptation, wherein the replacement value provider is configured to provide the replacement sample timing information considering a timing error information, or a quantity derived from the timing error information, over a longer time period when compared to a time period considered by the loop filter for a provision of the sample timing information.

A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented fast turn-on bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.

A circuit for estimating a time difference between a first signal and a second signal, the circuit comprising: a first signal line for receiving the first signal; a delay unit configured to receive the second signal and delay the second signal so as to provide a plurality of delayed versions of the second signal, each delayed version being delayed by a different amount of delay to the other delayed versions; a comparison unit configured to compare each of the delayed versions of the second signal with the first signal so as to identify which of the delayed versions of the second signal is the closest temporally matching signal to the first signal; and a difference estimator configured to estimate the time difference between the first and second signals in dependence on the identified delayed version.

A semiconductor circuit including a clocked comparator and an offset application circuit. The clocked comparator is configured to receive a first input signal and a second input signal from a host and compare the first input signal and the second input signal. The offset application circuit is configured to apply an offset to the first input signal. The clocked comparator is configured to be driven based on a reference clock provided from the host.

A circuit for performing clock recovery according to a received digital signal. The circuit includes at least an edge sampler and a data sampler for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock and data clock signals offset in phase from one another to the respective clock inputs of the edge sampler and the data sampler. A digital phase detector determines if the data clock is early, late or synchronized with respect to data value transitions in the digital signal, and based on that determination provides a phase adjustment signal to the clock signal supply circuit, which is operable to vary phases of the data and edge clock signals accordingly.

A clock recovery system includes: a sampler that samples reception data with 2N phase clocks and outputs 2NM sampling signals; a data selector that selects nM recovery signals from the 2NM sampling signals and outputs the nM recovery signals; a phase comparator that outputs, for each of the nM recovery signals, a phase comparison signal based on the recovery signal, a first sampling signal sampled with a first clock that leads by one or more phases from a sampling clock, and a second sampling signal sampled with a second clock that delays by one or more phases from the sampling clock; a controller that designates n based on a data rate of the reception data; and a multiphase clock generator that generates and outputs the 2N phase clocks based on the phase comparison signal and n.

A semiconductor apparatus includes a transmission device and a receiving device. The transmission device generates an output signal from a transmission signal in synchronization with a clock signal. The receiving device generates a reception signal from the output signal in synchronization with the clock signal and a delayed clock signal generated by delaying the clock signal by a preset time, based on an operating speed of the semiconductor apparatus.