Systems and methods are provided for low-power asynchronous data links. A receiver may obtain from signals, received from a transmitter over low-power asynchronous links, recovery information embedded into the signals at the transmitter, and may determine based on the recovery information, control parameters that may be used in configuring a control signal applied during processing of the signals. The signals may be processed based on the control signal, with the processing comprising extraction of data embedded in the signals at the transmitter. The transmitter may generate, based on an input datastream, signals configured for transmission to the receiver, over low-power asynchronous data links, and may embed into the signals, the recovery information that enables determining, at the receiver, parameters relating to the signals and/or to the generating of the signals. The control parameters may comprise parameters relating to the signals and/or processing of the signals at the transmitter.

A clock recovery system includes: a sampler that samples reception data with 2N phase clocks and outputs 2NM sampling signals; a data selector that selects nM recovery signals from the 2NM sampling signals and outputs the nM recovery signals; a phase comparator that outputs, for each of the nM recovery signals, a phase comparison signal based on the recovery signal, a first sampling signal sampled with a first clock that leads by one or more phases from a sampling clock, and a second sampling signal sampled with a second clock that delays by one or more phases from the sampling clock; a controller that designates n based on a data rate of the reception data; and a multiphase clock generator that generates and outputs the 2N phase clocks based on the phase comparison signal and n.

The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.

A receiver may include a plurality of receiving units connected with corresponding channels, and a clock data recovery unit connected with a sensing channel among the channels via a sensing line and connected with the receiving units via a common clock line. The receiving units may receive training pattern signals having the same transition direction through the channels in a training mode, and, in the training mode the clock data recovery unit may generate a phase-adjusted sampling clock signal so that a sampling time corresponds to a transition time of a training pattern signal of the sensing channel.

A controller area network receiver includes a measurement circuit, a filter circuit, and a frame detection circuit. The measurement circuit is coupled to a bit stream input terminal, and includes a timer circuit and error calculation circuitry. The timer circuit is coupled to the bit stream input terminal and a reference clock generator circuit. The error calculation circuitry is coupled to the timer circuit. The filter circuit is coupled to the measurement circuit, and includes error clipping control circuitry and clock period adjustment circuitry. The error clipping control circuitry is coupled to the error calculation circuitry. The clock period adjustment circuitry is coupled to the error calculation circuitry and the timer circuit. The frame detection circuit is coupled to the filter circuit and the bit stream input terminal.

Methods and systems for cross-protocol time synchronization may comprise, for example, in a premises-based network, receiving a signal that conforms to a data over cable service interface specification (DOCSIS) communications protocol. A global time of day (GTOD) clock may be extracted from the received signal. Communication on the premises-based network in accordance with a multimedia over cable alliance (MoCA) communications protocol may be synchronized based at least in part on the extracted GTOD clock. Communication in a third communications protocol may be synchronized, wherein the third communications protocol may include a home phoneline networking alliance (HPNA) standard, an IEEE 802.11x standard, and a non-public wireless network protocol. The extracted GTOD clock may comprise a GPS clock, GLONASS clock, and a Galileo clock. A second signal for extracting a GTOD may be received, such as a satellite signal, and may conform to a low Earth orbit satellite signal protocol.

Embodiments of this application provide a method for obtaining a phase detection signal in a clock recovery circuit and a phase detector, configured to obtain a correct phase detection signal. A phase detector obtains sampling sequences sent by an analog to digital converter ADC, where the sampling sequences are obtained by the ADC by sampling, an electrical signal received by the ADC, and the electrical signal carries a pre-configured training sequence; the phase detector calculates a correlation between the sampling sequences and a comparison sequence, to determine a first location and a second location, where the first location and the second location are locations of a starting point of the training sequence in the sampling sequences; and the phase detector obtains a phase detection signal based on a difference parameter of the first location and the second location.

A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented fast turn-on bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Methods and systems for cross-protocol time synchronization may comprise, for example, in a premises-based network, receiving a signal that conforms to a data over cable service interface specification (DOCSIS) communications protocol. A global time of day (GTOD) clock may be extracted from the received signal. Communication on the premises-based network in accordance with a multimedia over cable alliance (MoCA) communications protocol may be synchronized based at least in part on the extracted GTOD clock. Communication in a third communications protocol may be synchronized, wherein the third communications protocol may include a home phoneline networking alliance (HPNA) standard, an IEEE 802.11x standard, and a non-public wireless network protocol. The extracted GTOD clock may comprise a GPS clock, GLONASS clock, and a Galileo clock. A second signal for extracting a GTOD may be received, such as a satellite signal, and may conform to a low Earth orbit satellite signal protocol.