Patent classifications
H04L7/0079
PAM4 transceivers for high-speed communication
The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.
Independent packet detection method using synchronization words with orthogonality and receiver therefor
A receiver performs independent packet detection using synchronization words with orthogonality when multiple signals on which frequency-shift keying is performed coexist. The receiver includes a frequency demodulator generating a quasi-amplitude modulation signal that has a value proportional to frequency shift from the first signal or second signal being received, a sign discriminator discriminating a sign of the generated quasi-amplitude modulation signal, and a multi-binary correlator calculating a first correlation value which is a binary correlation value between the discriminated sign and a first synchronization word and calculating a second correlation value which is a binary correlation value between the discriminated sign and a second synchronization word.
Time synchronisation method, insensitive to power variations, associated receiver and computer program
A method of synchronising a communication signal entering into a receiver. Each frame of the signal includes a learning symbol formed of N repetitions of a learning sequence. The method includes the determination of a total correlation signal by correlating the input signal with a correlation symbol formed of N repetitions of a correlation sequence corresponding to all or part of the learning sequence and duration t.sub.sc, and the determination of a partial correlation signal by correlating the input signal with the correlation sequence. A peak of the total correlation signal is identified at an instant t.sub.pct. At least one threshold is defined from the power of the peak of the total correlation signal, and the power of the partial correlation signal is compared here to the instants t.sub.pctk*t.sub.sc, with k a whole number between 0 and N1.
PROTOCOL SYNCHRONIZATION FOR HARQ
A method and apparatus according to the present invention addresses and/or prevents lost protocol synchronization in HARQ systems caused by ACK/NACK errors. One embodiment detects lost synchronization errors for NDI-based retransmission protocols and restores synchronization by sending an explicit RESET message. In response to the RESET message, the transmitter aborts the transmission of a current PDU and transmits a new PDU and corresponding NDI. Another embodiment prevents protocol synchronization errors by sending scheduling grants on a packet by packet basis. The receiver sends a subsequent explicit scheduling grant to the transmitter based on an error evaluation of a received PDU. The transmitter will not send the next PDU unless it receives the subsequent explicit scheduling grant.
SIGNAL TRANSMITTING AND RECEIVING DEVICE AND BIDIRECTIONAL COMMUNICATION SYSTEM
A bidirectional communication system 1 comprises a signal transmitting and receiving device 10 and a signal transmitting and receiving device 20 that perform bidirectional communication via a transmission path 30. The signal transmitting and receiving device 20 comprises a driver 21, a filter 22, a receiver 23, and a controller 24. The receiver 23 recovers a clock signal by performing frequency locking on a training pattern signal output through the filter 22, and outputs a recovered clock to the controller 24. The controller 24 receives the recovered clock output from the receiver 23, controls a cutoff frequency of the filter 22, and controls an operation of the driver 21 based on a frequency information of the recovered clock signal.
PHASE CONTROL IN DISTRIBUTED ARRAYS
A mm-wave signal generation technique that provides background phase tuning and self-alignment between adjacent sources. This technique is based on direct monitoring of the mm-wave signal and provides phase tuning through a baseband feedback loop. The techniques may be advantageous for phase alignment of large-scale mm-wave phased arrays.
System and method for drift compensation in data communications
A method and system are provided for drift compensation, providing a live data approach to sampler offset calibration, such as for voltage and/or temperature (VT) drift. A serializer/deserializer (SerDes) system includes a SerDes receiver and receiver logic, the receiver logic including a forward error correction (FEC) module. A drift compensation device, or drift compensation engine, receives live error corrections from the FEC module based on FEC operations performed on live traffic passing through the SerDes receiver. A drift compensation command is provided to a data sampler in the SerDes receiver, to adjust a sampling voltage of the data sampler. When the system includes a plurality of data samplers, the drift compensation device determines the data sampler with which an error correction is associated. The drift compensation command can be sent after a threshold criterion is satisfied, such as completion of a statistics collection period, or a threshold number of corrections.
Multipath clock and data recovery
Multipath clock and data recovery circuits and multipath I/O devices are described that operate to provide flexible I/O paths for serial data communications. Active unidirectional components such as a clock and data recovery circuit may be used to implement different I/O paths. Bandwidth and signal degradation for high-speed serial data transmission is reduced.
Optimized PHY Frame Structure for OFDM Based Narrowband PLC
A method of operating a communication system is disclosed. The method includes forming a data frame having plural orthogonal frequency division multiplex (OFDM) symbols. A first set of preamble subcarriers is allocated to at least one of the OFDM symbols. A second set of data subcarriers is allocated to said at least one of the OFDM symbols.
ENHANCED FAILOVER HANDLING IN DATA CENTERS
Described herein are methods, systems, and software for accommodating failover of a content node in a content delivery network. In one example, a method of operating a content node includes receiving a communication for an end user device from a control node, wherein an interrupted content node previously handled the communication. The method further includes determining if the communication includes a synchronization packet and identifying connection information for the communication. The method also provides, if the communication includes a synchronization packet, accepting the communication and handling delivery for the end user device. The method also includes, if the communication does not include the synchronization packet, determining if a match exists between the connection information for the communication and connection information stored in a flow table, and handling the communication based on the match.