A data communication framing scheme of a bit stream that is divided among a plurality of discrete physical frames, each physical frame is of a definite number of symbols in duration, each symbol is associated with at least one sub-carrier in a plurality of sub-carriers, the physical frame is partitioned in time into at least an uplink zone and a downlink zone, the data framing scheme comprising a logical frame having a logical frame start position that is offset by a rational number of said symbols from a reference symbol, said reference symbol is selected from said definite number of symbols, wherein said logical frame extends in time to coincide with at least part of the duration of said physical frame and at least part of the duration of another physical frame in said plurality of discrete physical frames.

The method and apparatus for detecting in a receiver a transmitter local time, comprising determining a reference time for the transmitter local time; receiving from the transmitter a transmission time duration signal that elapsed on the transmitter since the reference time for the transmitter local time; and determining the transmitter local time based on the reference time for the transmitter local time and the received transmitter time duration. A time stamp signal based on the transmitter local time signal is generated at the receiver and is superimposed on the sensor data stream transmitted to the receiver. Consequently, the advantage is provided that a data stream can be transmitted without the incorporation of any time stamp.

Clock recovery techniques (CRT) useful in a wide variety of communication systems based on wireless, optical and wireline links, include: a hybrid PLL (HPLL) enabling 1-50,000 frequency multiplication with very low output jitter independent of reference clock quality, a software controlled clock synthesizer (SCCS) for high accuracy phase & frequency synthesis producing synchronized low jitter clock from external time referencing clocks, waveforms or messages, receiver synchronization techniques (RST) contributing more accurate synchronization of receiver clock to OFDM composite frame combined with much faster acquisition time and better stability of the receiver clock.

A symbol clock recovery circuit for recovering a symbol clock in an M-ary pulse position modulation (PPM) signal. The recovery circuit includes a largest magnitude comparison circuit that selects a largest magnitude signal value from a group of M signal values aligned with a hypothesis symbol boundary location and the average of that largest magnitude value is compared with a threshold, or with results from other boundary location hypotheses, or with both, to determine the true position of the symbol boundary.

Techniques for pilot-aided carrier frequency and phase synchronization may use a three-pass process. In a first pass, initial frequency offset may be addressed, and a frame start time may be established. In a second pass, a fine frequency correction may be performed. In a third pass, phase variation may be tracked and corrected using a minimum set of pilot symbols.

A method comprising modulating a plurality of synchronized signals by an orthogonal probe sequence (OPS) to generate a plurality of modulated synchronized signals, wherein the OPS comprises a zero element (0-element) column that indicates a start or an end of the OPS, and concurrently transmitting, using one or more transmitters, the plurality of modulated synchronized signals over a duration of a number of discrete multi-tone (DMT) symbols, wherein each of the plurality of modulated synchronized signals is intended for one of a plurality of receivers that are remotely coupled to the one or more transmitters via a vectored group of subscriber lines, and wherein the 0-element column causes all of the plurality of modulated synchronized signals to have a zero-amplitude during a first or a last of the DMT symbols.

A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.

A method for processing a radio signal includes producing first and second streams of audio samples; decimating the first and second streams of audio samples to produce first and second streams of decimated streams of audio samples; estimating a first offset value between corresponding samples in the first and second streams of decimated streams of audio samples; shifting one of the first and second streams of audio samples by a first shift value; decimating the first and second streams of audio samples to produce third and fourth streams of decimated audio samples; estimating a second offset value; determining a final offset value based on an intersection of ranges of valid results of the first and second offset values; and shifting one of the first and second streams of audio samples by the final offset value to align the first and second streams of audio samples.

A design method for a phase-locked loop comprises: a controlled-frequency oscillator; a phase comparator, to determine a phase difference between an output signal of the controlled-frequency oscillator and a reference signal; a corrector to receive as input a signal representative of the phase difference and to generate at its output a first correction signal; at least one second corrector, to receive as input a signal representative of or affected by a phase noise of the reference signal or of the output signal of the controlled-frequency oscillator and to generate at its output a second correction signal; and a circuit for generating a slaving signal for the controlled-frequency oscillator on the basis of the first and second correction signals; the method using the H-infinity method. Method for fabricating such a loop comprising a design step implementing this method. Phase-locked loop thus obtained.

Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.