Various example embodiments relate to partial data transmission. A transmitter may receive at least one dataset for transmission. The dataset may be one of a plurality of datasets known to the transmitter and a receiver or to be signaled to the receiver. The transmitter may determine a first portion of the dataset. The size of the first portion may be determined based on a battery level indicator, a latency level associated with the dataset, a radio condition, or a network load. The receiver may recognize the dataset based on the first portion and/or at least one second portion transmitted by the transmitter. Apparatuses, methods, and computer programs are disclosed.

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

A device providing concurrent audio streaming to multiple wireless audio output devices may include at least one processor configured to receive a user selection of at least two paired audio output devices. The at least one processor may be further configured to connect to each of the at least two of the paired audio output devices. The at least one processor may be further configured to synchronize at least one audio output synchronization parameter across each of the at least two of the paired audio output devices. The at least one processor may be further configured to concurrently stream a respective audio stream to each of the at least two of the paired audio output devices.

Various embodiments provide for calibrating one or more clock signals for a serializer, which can be used with a circuit for data communications, such as serializer/deserializer (SerDes) communications. In particular, for a serializer operating based on a plurality of clock signals, some embodiments provide for calibration of one or more of the plurality of clock signals by adjusting a duty cycle of one or more clock signals, a delay of one or more clock signals, or both.

A timing system including timing circuitry which includes an arming queue, a clock work queue, and a clock completion queue. At least the clock work queue is to provide timing information, and the arming queue is to arm the clock work queue. Related apparatus and methods are also provided.

A transmitter is configured to transmit a series of command signals and a series of data signals. The transmitter includes a serializer and a multiplexer. The serializer is configured to generate the series of data signals. The multiplexer, coupled to the serializer, is configured to selectively output the series of command signals or the series of data signals

Examples described herein relate to a first central processing unit (CPU) node to generate time stamp counter (TSC) values based on a first clock signal and a second CPU node to generate TSC values based on a second clock signal. In some examples, the first CPU node is to determine at least one network timer time stamp based on the TSC values based on the first clock signal and the second CPU node is to determine at least one network timer time stamp based on the TSC values based on the second clock signal. In some examples, determine at least one network timer time stamp based on the TSC values based on the first clock signal is based on (i) a relationship between the first clock signal and a network interface device main timer and (ii) a relationship between a network timer source and the network interface device main timer.

A master integrated circuit (IC) chip includes transmit circuitry and receiver circuitry. The transmit circuitry includes a timing signal generation circuit to generate a first timing signal, and a driver to transmit first data in response to the first timing signal. A timing signal path routes the first timing signal in a source synchronous manner with the first data. The receiver circuitry includes a receiver to receive second data from a slave IC chip, and sampling circuitry to sample the second data in response to a second timing signal that is derived from the first timing signal.

A data transmission device of an embodiment includes a buffer, a first determination circuit, a first flip-flop, a second flip-flop, and a second determination circuit. The buffer holds input data of a predetermined bit width. The first determination circuit determines whether or not the input data is held in the buffer. The first flip-flop receives output of the first determination circuit as input and operates at one of a rising edge and a falling edge of a second clock signal which is asynchronous with the first clock signal. The second flip-flop receives output of the first flip-flop as input and operates at another of the rising edge and the falling edge of the second clock signal. The second determination circuit determines an error based on a request signal which is synchronized with the second clock signal and output of the second flip-flop.

Ultra-Wideband (UWB) technology exploits modulated coded impulses over a wide frequency spectrum with very low power over a short distance for digital data transmission. Today's leading edge modulated sinusoidal wave wireless communication standards and systems achieve power efficiencies of 50 nJ/bit employing narrowband signaling schemes and traditional RF transceiver architectures. However, such designs severely limit the achievable energy efficiency, especially at lower data rates such as below 1 Mbps. Further, it is important that peak power consumption is supportable by common battery or energy harvesting technologies and long term power consumption neither leads to limited battery lifetimes or an inability for alternate energy sources to sustain them. Accordingly, it would be beneficial for next generation applications to exploit inventive transceiver structures and communication schemes in order to achieve the sub nJ per bit energy efficiencies required by next generation applications.