Embodiments include systems and methods for applying a controllable early/late offset to an at-rate clock data recovery (CDR) system. Some embodiments operate in context of a CDR circuit of a serializer/deserializer (SERDES). For example, slope asymmetry around the first precursor of the channel pulse response for the SERDES can tend to skew at-rate CDR determinations of whether to advance or retard clocking. Accordingly, embodiments use asymmetric voting thresholds for generating each of the advance and retard signals in an attempt to de-skew the voting results and effectively tune the CDR to a position either earlier or later than the first precursor zero crossing (i.e., h(−1)=0) position. This can improve link margin and data recovery, particularly for long data channels and/or at higher data rates.

Embodiments include systems and methods for applying a controllable early/late offset to an at-rate clock data recovery (CDR) system. Some embodiments operate in context of a CDR circuit of a serializer/deserializer (SERDES). For example, slope asymmetry around the first precursor of the channel pulse response for the SERDES can tend to skew at-rate CDR determinations of whether to advance or retard clocking. Accordingly, embodiments use asymmetric voting thresholds for generating each of the advance and retard signals in an attempt to de-skew the voting results and effectively tune the CDR to a position either earlier or later than the first precursor zero crossing (i.e., h(−1)=0) position. This can improve link margin and data recovery, particularly for long data channels and/or at higher data rates.

The present disclosure relates to a data driving device and a method of driving the data driving device and, more particularly, to a data driving device and a method of driving the same in which a tuning of a set value of an internal circuit is automatically performed.

The present disclosure relates to a data driving device and a method of driving the data driving device and, more particularly, to a data driving device and a method of driving the same in which a tuning of a set value of an internal circuit is automatically performed.

A method for compensating for a sampling clock-offset includes calculating a positive threshold and a negative threshold of pulse-shaped data symbols to be received, calculating a positive sum ratio and a negative sum ratio from received samples, and compensating for a sampling clock-offset in response to the positive sum ratio being less than or equal to the positive threshold and the negative sum ratio being less than or equal to the negative threshold.

A method for compensating for a sampling clock-offset includes calculating a positive threshold and a negative threshold of pulse-shaped data symbols to be received, calculating a positive sum ratio and a negative sum ratio from received samples, and compensating for a sampling clock-offset in response to the positive sum ratio being less than or equal to the positive threshold and the negative sum ratio being less than or equal to the negative threshold.

Certain implementations of the disclosed technology may include systems and methods for data alignment without requiring an external synchronizing trigger. A method is provided that can include receiving a signal that represents a plurality of frames, each of the plurality of the frames include an optional data portion and a predetermined portion. The method includes sampling and buffering at least a portion of the received signal to produce a buffered digital sequence. The method includes processing, by a sequence alignment module, the buffered digital sequence using a known sequence, where the known sequence corresponds to the predetermined portion. The method includes determining, using the sequence alignment module, respective positions of the buffered digital sequence corresponding to the known sequence, comparing the known sequence with the buffered digital sequence at the respective determined positions, and outputting one or more parameters based at least in part on the comparing.

In an embodiment, a receiver detects a timing error between a transmitter clock at a transmitter and a receiver clock at a receiver associated with an exchange of CPM signals. The receiver phase aligns input samples of a candidate received signal over a time window based on a rotating signal corresponding to a phase progression of the candidate received signal. The receiver generates first and second partial sums of the phase-aligned input samples that are accumulations of phase-aligned input samples corresponding to modulation symbols that contribute positive and negative phases, respectively, to the phase progression. The receiver determines a phase difference between the first and second partial sums, and generates a timing-error metric that is indicative of a timing error between the transmitter clock and the receiver clock based at least in part upon the determined phase difference.

A first flip-flop outputs a first output signal as a first switch signal that controls a first switch. A second flip-flop outputs a second output signal based on a clock signal and the first output signal. A first inverting circuit generates a first inverted signal obtained by inverting the first output signal. A second AND circuit outputs a signal that is an AND of the first inverted signal and the second output signal, as a second switch signal that controls a second switch.

A first flip-flop outputs a first output signal as a first switch signal that controls a first switch. A second flip-flop outputs a second output signal based on a clock signal and the first output signal. A first inverting circuit generates a first inverted signal obtained by inverting the first output signal. A second AND circuit outputs a signal that is an AND of the first inverted signal and the second output signal, as a second switch signal that controls a second switch.