An example method includes: obtaining sinusoidal signals comprising components of a first time-domain signal; shifting phases of the sinusoidal signals by amounts corresponding to a specified time-shift to produce phase-shifted signals, and converting the phase-shifted signals to the time domain to produce time-shifted signals. The shifting may be performed to more closely align an envelope of the first time-domain signal with an envelope of a second time-domain signal.

Disclosed herein are systems and methods for clock sustain in a two-wire communication systems and applications thereof. In some embodiments, in a clock sustain state, slave nodes with processors and digital to analog converters (DACs) may be powered down efficiently in the event of lost bus communication. For example, when the bus loses communication and a reliable clock cannot be recovered by the slave node, the slave node may enter the sustain state and, if enabled, signals this event to a general purpose input/output (GPIO) pin. In the clock sustain state, the slave node phase lock loop (PLL) may continue to run for a predetermined number of SYNC periods, while attenuating the inter-integrated circuit transmit (I2S DTXn) data from its current value to 0. After the predetermined number of SYNC periods, the slave node may reset and reenter a power-up state.

Systems, methods, and apparatus for synchronizing timing in devices coupled to a data communication link are disclosed. In one example, a first device programs a future system time value in a second device. The first device launches a low-latency trigger signal that causes the future system time value to be loaded into a timer of the second device when a timer of the first device matches the future system time value. The second device measures phase difference between the trigger signal and edges of a clock signal used for timing in the second device. The phase difference is measured using an oversampling clock that provides a desired measurement reliability. The measured phase difference permits the first device to accurately determine system time as applied to the second device. The trigger signal can be provided on existing pins used by first and second devices in accordance with communication protocols and specifications.

Systems, methods, and apparatus for synchronizing timing in devices coupled to a data communication link are disclosed. In one example, a first device programs a future system time value in a second device. The first device launches a low-latency trigger signal that causes the future system time value to be loaded into a timer of the second device when a timer of the first device matches the future system time value. The second device measures phase difference between the trigger signal and edges of a clock signal used for timing in the second device. The phase difference is measured using an oversampling clock that provides a desired measurement reliability. The measured phase difference permits the first device to accurately determine system time as applied to the second device. The trigger signal can be provided on existing pins used by first and second devices in accordance with communication protocols and specifications.

Methods and apparatus for generating a standard pattern for data signals from a set of multiple data signals are provided. The standard pattern consists of a signal length, a centerline, an upper limit, and a lower limit. One of methods comprises, receiving first and second data signals, determining a standard pattern length for each of the first and second data signals, sampling each of the first and second data signals by as much as the determined standard pattern length, aligning the sampled first and second data signals, and generating a standard pattern for the first and second data signals by overlapping the aligned first and second data signals, wherein the generated standard pattern is a standard pattern having reflected thereinto upper and lower limit ranges that are determined using levels of the aligned first and second data signals.

Methods and apparatus for generating a standard pattern for data signals from a set of multiple data signals are provided. The standard pattern consists of a signal length, a centerline, an upper limit, and a lower limit. One of methods comprises, receiving first and second data signals, determining a standard pattern length for each of the first and second data signals, sampling each of the first and second data signals by as much as the determined standard pattern length, aligning the sampled first and second data signals, and generating a standard pattern for the first and second data signals by overlapping the aligned first and second data signals, wherein the generated standard pattern is a standard pattern having reflected thereinto upper and lower limit ranges that are determined using levels of the aligned first and second data signals.

Approaches for clock synchronization in digital video environments. In an embodiment, an encoder/transcoder calculates a ratio between a system clock and a source clock. The source clock is used by a source device to encode or transcode digital video. The system clock is used by the encoder/transcoder. After the encoder/transcoder receives the digital video from the source device, the encoder/transcoder uses the calculated ratio to create a recovered clock. The recovered clock is locked to a frequency of the source clock but not to the phase of the source clock. The encoder/transcoder uses the recovered clock to encode or transfer the digital video received from the source device. The encoder/transcoder ensures that the frequency of the recovered clock does not change faster than a certain rate, e.g., 0.075 Hz/second.

A communication apparatus is one of a plurality of communication apparatuses included in a communication system where a first communication apparatus transmits data via a transmission path in synchronization with communication by a second communication apparatus. The communication apparatus includes a switching element setting a signal level on the transmission path to a dominant level by being turned on; a driving circuit driving the switching element. and a control circuit giving an on command that instructs the driving circuit to turn the switching element on in response to an edge at which a signal level on the transmission path changes from a recessive level to a dominant level being detected. The driving circuit or the control circuit is further configured to shorten a delay time from when the edge is detected to when the switching element is turned on.

A communication apparatus is one of a plurality of communication apparatuses included in a communication system where a first communication apparatus transmits data via a transmission path in synchronization with communication by a second communication apparatus. The communication apparatus includes a switching element setting a signal level on the transmission path to a dominant level by being turned on; a driving circuit driving the switching element. and a control circuit giving an on command that instructs the driving circuit to turn the switching element on in response to an edge at which a signal level on the transmission path changes from a recessive level to a dominant level being detected. The driving circuit or the control circuit is further configured to shorten a delay time from when the edge is detected to when the switching element is turned on.

Systems, devices, and methods related to selecting a sample phase of a signal are disclosed. A method includes sampling a signal including a plurality of symbols with a plurality of different sample phases to obtain sample values of each of the plurality of symbols at each of the plurality of different sample phases. The signal is received from a shared transmission medium. The method also includes determining an edge sample phase of the plurality of different sample phases that corresponds to edges of the symbols based on the sample values. The method further includes determining a center sample phase of the plurality of different sample phases based on the determined edge sample phase, and using the determined center sample phase to determine values of the symbols.