The present invention provides a CDR circuit including a first phase detector, a controller and a phase filter. In the operations of the CDR, the first phase detector is configured to compare a phase of an input signal and a phase of a clock signal to generate a first phase detection result. The controller is configured to generate a control signal according to the first phase detection result. The phase filter is configured to receive the control signal and an auxiliary signal to generate the clock signal, wherein the auxiliary signal is generated according to the first phase detection result.

The present invention provides a CDR circuit including a first phase detector, a controller and a phase filter. In the operations of the CDR, the first phase detector is configured to compare a phase of an input signal and a phase of a clock signal to generate a first phase detection result. The controller is configured to generate a control signal according to the first phase detection result. The phase filter is configured to receive the control signal and an auxiliary signal to generate the clock signal, wherein the auxiliary signal is generated according to the first phase detection result.

Provided is a management device or the like that can flexibly set a task cycle of a master device. The management device is a management device that manages a network including a master device and a slave device connected to the master device, and comprises: a transmission delay time prediction unit which predicts a transmission delay time on the basis of network configuration information and node information; a transmission delay time measurement unit which measures the transmission delay time in the network; and a transmission delay time setting unit which presents to the user, a predicted value predicted by the transmission delay time prediction unit and a measured value measured by the transmission delay time measurement unit, and sets a cycle setting transmission delay time for setting a task cycle in which the master device transmits a signal to the slave device, according to the selection operation of the user.

Provided is a management device or the like that can flexibly set a task cycle of a master device. The management device is a management device that manages a network including a master device and a slave device connected to the master device, and comprises: a transmission delay time prediction unit which predicts a transmission delay time on the basis of network configuration information and node information; a transmission delay time measurement unit which measures the transmission delay time in the network; and a transmission delay time setting unit which presents to the user, a predicted value predicted by the transmission delay time prediction unit and a measured value measured by the transmission delay time measurement unit, and sets a cycle setting transmission delay time for setting a task cycle in which the master device transmits a signal to the slave device, according to the selection operation of the user.

Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

A network transceiver device is provided, including at least two variable gain amplifiers (VGAs), and at least two sets of analog digital converters (ADCs), each set including ADCs coupled to an output of one of the VGAs, the sets being arranged in VGA-specific channels. The device includes a plurality of feed-forward equalizers (FFEs), each FFE being coupled to receive an output of one of the ADCs in one of the VGA-specific channels. Each FFE is configured to adaptively equalize the output received from the ADCs utilizing a first equalization coefficient subset with coefficient values that are common to all FFEs, and a second equalization coefficient subset that is channel specific and that has a first set of coefficient values for a first VGA-specific channel and a second set of coefficient values for a second VGA-specific channel, the sets of coefficient values being computed independently.

A network transceiver device is provided, including at least two variable gain amplifiers (VGAs), and at least two sets of analog digital converters (ADCs), each set including ADCs coupled to an output of one of the VGAs, the sets being arranged in VGA-specific channels. The device includes a plurality of feed-forward equalizers (FFEs), each FFE being coupled to receive an output of one of the ADCs in one of the VGA-specific channels. Each FFE is configured to adaptively equalize the output received from the ADCs utilizing a first equalization coefficient subset with coefficient values that are common to all FFEs, and a second equalization coefficient subset that is channel specific and that has a first set of coefficient values for a first VGA-specific channel and a second set of coefficient values for a second VGA-specific channel, the sets of coefficient values being computed independently.

The present disclosure concerns a method of synchronization of data packet transmission (P1, P2, P3) in a network (N), including and/or initiating the acts of: Receiving (S1), e.g. from a terminal device (T1, T2, T3) of the network (N), one or more data packets (P1, P2, P3) after a threshold time interval (tt) of a periodic transmission window (RT, BE), wherein the threshold time interval (tt) is arranged at the beginning of said periodic transmission window (RT, BE), and Forwarding (S2) the data packet (P1, P2, P3) in a subsequent transmission window (RT, BE), preferably directly after the transmission window in which the data packet (P1, P2, P3) was received, within the threshold time interval (tt) of the transmission window (RT, BE).

The present disclosure concerns a method of synchronization of data packet transmission (P1, P2, P3) in a network (N), including and/or initiating the acts of: Receiving (S1), e.g. from a terminal device (T1, T2, T3) of the network (N), one or more data packets (P1, P2, P3) after a threshold time interval (tt) of a periodic transmission window (RT, BE), wherein the threshold time interval (tt) is arranged at the beginning of said periodic transmission window (RT, BE), and Forwarding (S2) the data packet (P1, P2, P3) in a subsequent transmission window (RT, BE), preferably directly after the transmission window in which the data packet (P1, P2, P3) was received, within the threshold time interval (tt) of the transmission window (RT, BE).

Provided are a method and an apparatus for optimizing the performance of an optical transceiver, and the gist is as follows: receiving an optical input and converting the optical input into electrical signals; receiving a performance value and a reference clock of the electrical signals from a DSP part; generating a plurality of clocks by using the reference clock; determining ADC sampling timings of a plurality of ADCs on the basis of phases of the plurality of clocks applied to the plurality of ADCs; and compensating, on the basis of the determined ADC sampling timings, for differences in physical length between output signals of the plurality of ADCs.