A packaged circuit including a digital controller, a port physical layer and a digital coding circuit is provided. The digital controller outputs digital data in parallel via a parallel data channel, and the digital data includes a plurality of data bits. The port physical layer includes a clock generator, and outputs a data signal according to the data bits. The clock generator outputs a clock signal to the digital controller. The digital coding circuit is coupled to the digital controller and the port physical layer, and receives the digital data and the clock signal. The digital coding circuit codes the clock signal to generate a plurality of clock bits, and outputs the clock bits to the port physical layer. The port physical layer converts the clock bits into an output clock and outputs the output clock.

A method for receiving and transmitting synchronization signal is provided. The method is applicable to a wireless communication device. The wireless communication device has a local timing. The method includes the following steps. Receive at least one synchronization signal. If a signal power of at least one of the at least one synchronization signal is greater than or equal to a signal power threshold, select one of the at least one synchronization signal as a reference synchronization signal according to a priority rule, and synchronize the local timing to the reference synchronization signal. If the signal power of each the synchronization signal is less than the signal power threshold, send a local synchronization signal according to the local timing. If the reference synchronization signal meets a forwarding criterion, forward the reference synchronization signal, wherein the forwarding criterion includes a power constraint and a hop count constraint.

The present technology relates to a data processing apparatus and a data processing method that can reduce errors of time arising from accuracy of time information. The data processing apparatus generates signaling including time information having accuracy of time according to a frame length of a physical layer frame and processes the signaling so as to be included into a preamble of the physical layer frame to make it possible to reduce errors of time arising from time information. The present technology can be applied, for example, to a transmitter compatible with a broadcasting method of ATSC3.0 and so forth.

The present technology relates to a data processing apparatus and a data processing method that can reduce errors of time arising from accuracy of time information. The data processing apparatus generates signaling including time information having accuracy of time according to a frame length of a physical layer frame and processes the signaling so as to be included into a preamble of the physical layer frame to make it possible to reduce errors of time arising from time information. The present technology can be applied, for example, to a transmitter compatible with a broadcasting method of ATSC3.0 and so forth.

Provided is a system for time synchronization between a server and an Internet-of-Things (IoT) device. The system may include a server configured to broadcast a time-point synchronization signal including absolute time point information; and an IoT device configured to receive the broadcast time-point synchronization signal and calculate absolute time point information by using the absolute time point information included in the time-point synchronization signal, computation time information according to an internal computation operation, and transmission time information required to receive the time-point synchronization signal.

Provided is a system for time synchronization between a server and an Internet-of-Things (IoT) device. The system may include a server configured to broadcast a time-point synchronization signal including absolute time point information; and an IoT device configured to receive the broadcast time-point synchronization signal and calculate absolute time point information by using the absolute time point information included in the time-point synchronization signal, computation time information according to an internal computation operation, and transmission time information required to receive the time-point synchronization signal.

A wireless receiver is disclosed. The wireless receiver includes a phased array antenna panel having a plurality of antennas, and a low resolution analog-to-digital (A/D) converter coupled to each of the plurality of antennas, where the low resolution A/D converter is configured to provide a digital output based on comparing a reference value with a sum of noise value and signal value of an analog input received by the corresponding one of the plurality of antennas. Noise signals received by the plurality of antennas are uncorrelated, and a signal to noise ratio (SNR) of the analog input can be less than one. The low resolution A/D converter can be a one-bit A/D converter. The one-bit A/D converter can be a comparator receiving the sum of noise value and signal value as one comparator input, and receiving the reference value as another comparator input.

In order to address the needs of narrow band communication, eNB-based processing and/or UE-based processing is provided to achieve robust detection of cell ID and SFN timing location using NB-SSS. A base station constructs a NB-SSS signal using a root index of a Zadoff-Chu (ZC) sequence, a scrambling code, a cyclic shift or phase ramping sequence, and an interleaving sequence, wherein a combination of the ZC root index, the scrambling code index, the cyclic shift or phase ramping sequence index, and the interleaving sequence index signals information for a cell identifier (e.g., PCID) and frame timing. The ZC sequence used may be a long ZC sequence constructed to span a total number of tones allocated to an SSS sequence or may be a concatenation of multiple ZC sequences, wherein the concatenated ZC sequences span a total number of tones allocated to an SSS sequence.

A display is disclosed where in an optimization mode, the controller transmits a first lock signal having a pulse waveforms to a first source driver circuit among source driver circuits, receives a second lock signal having pulse waveforms from a last source driver circuit that receives the first lock signal, and transmits phase loop fixed data for recovering a frequency and a phase of a clock to each of the source driver circuits when the second lock signal is received, and in the display mode, the controller transmits a first lock signal having a preset voltage level to the first source driver circuit, receives a second lock signal having a plurality of preset voltage levels from a last source driver circuit, and supplies an image signal and control data to each of the source driver circuits when the second lock signal is received.

A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2.sup.N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.