In operation, packets traverse the packet processing data structure, and the network processing represented by each object in the data structure is applied to each packet. From time to time, the packet processing data structure may need to be updated. Embodiments of the present disclosure provide for lock-free updating of a packet processing data structure by means of epoch-based garbage collection. In embodiments, a particular past packet processing epoch is considered to be no longer referenced by any cores when the sequence numbers recorded in each said memory location are different to the sequence number of that particular past packet processing epoch. The deletion thread checks both whether a past epoch is being referenced by any packets and whether it is being reference by any cores. Thus memory is safely freed without having any impact on any packet processing which may be occurring in parallel to the deletion thread.

A parsing component includes m parsing units. At least one parsing unit in them parsing units includes a fixed parsing module and a configurable parsing module. The fixed parsing module stores fixed protocol content. The configurable parsing module is configured to configure protocol content in the configurable parsing module based on obtained content configuration information. Each parsing module in the fixed parsing module and the configurable parsing module is configured to parse a packet based on the protocol content in the parsing module. A target parsing unit is configured to separately parse, by using a fixed parsing module in the target parsing unit and a configurable parsing module in the target parsing unit, a packet input into the target parsing unit. This application helps improve parsing efficiency of the parsing component.

Various embodiments of a scanning engine are described. In some embodiments, the scanning engine comprises discovery components associated with different Internet providers and/or protocol detection components associated with the different Internet providers. When a first discovery component associated with a first Internet provider does not receive a response from a port at an Internet address, then a second discovery component associated with a second Internet provider sends packets to that port at that Internet address to attempt to elicit a response. When a first protocol inspection component associated with a first Internet provider is not able to communicate with a port at an Internet address, then it provides information that can be obtained by a second protocol inspection component associated with a second Internet provider. That second protocol inspection component attempts to communicate with the port at the Internet address through the second Internet provider using various communication protocols.

Various embodiments of a scanning engine are described. In some embodiments, the scanning engine comprises discovery components associated with different Internet providers and/or protocol detection components associated with the different Internet providers. When a first discovery component associated with a first Internet provider does not receive a response from a port at an Internet address, then a second discovery component associated with a second Internet provider sends packets to that port at that Internet address to attempt to elicit a response. When a first protocol inspection component associated with a first Internet provider is not able to communicate with a port at an Internet address, then it provides information that can be obtained by a second protocol inspection component associated with a second Internet provider. That second protocol inspection component attempts to communicate with the port at the Internet address through the second Internet provider using various communication protocols.

A representative system, apparatus, method and protocol are disclosed for data communication between chiplets or SOCs on a common interposer. A representative system comprises: an interposer; a first integrated circuit arranged on the interposer, the first integrated circuit comprising a first common protocol interface circuit; a communication link coupled to the first common protocol interface circuit; and a second integrated circuit arranged on the interposer, the second integrated circuit comprising a second common protocol interface circuit coupled to the communication link to form a serial protocol interface between the first common protocol interface circuit and the second common protocol interface circuit. Serial data and control packets and parallel data and control packets having specified, ordered fields are also disclosed.

A representative system, apparatus, method and protocol are disclosed for data communication between chiplets or SOCs on a common interposer. A representative system comprises: an interposer; a first integrated circuit arranged on the interposer, the first integrated circuit comprising a first common protocol interface circuit; a communication link coupled to the first common protocol interface circuit; and a second integrated circuit arranged on the interposer, the second integrated circuit comprising a second common protocol interface circuit coupled to the communication link to form a serial protocol interface between the first common protocol interface circuit and the second common protocol interface circuit. Serial data and control packets and parallel data and control packets having specified, ordered fields are also disclosed.

The embodiments herein describe a 3D SmartNIC that spatially distributes compute, storage, or network functions in three dimensions using a plurality of layers. That is, unlike current SmartNIC that can perform acceleration functions in a 2D, a 3D Smart can distribute these functions across multiple stacked layers, where each layer can communicate directly or indirectly with the other layers.

According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.

According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.

A novel algorithm for packet classification that is based on a novel search structure for packet classification rules is provided. Addresses from all the containers are merged and maintained in a single Trie. Each entry in the Trie has additional information that can be traced back to the container from where the address originated. This information is used to keep the Trie in sync with the containers when the container definition dynamically changes.