In operation, packets traverse the packet processing data structure, and the network processing represented by each object in the data structure is applied to each packet. From time to time, the packet processing data structure may need to be updated. Embodiments of the present disclosure provide for lock-free updating of a packet processing data structure by means of epoch-based garbage collection. In embodiments, a particular past packet processing epoch is considered to be no longer referenced by any cores when the sequence numbers recorded in each said memory location are different to the sequence number of that particular past packet processing epoch. The deletion thread checks both whether a past epoch is being referenced by any packets and whether it is being reference by any cores. Thus memory is safely freed without having any impact on any packet processing which may be occurring in parallel to the deletion thread.

At least a packet header of a packet received by a network device is provided to a programmable header alteration engine that includes a hardware input processor implemented in hardware and a programmable header alteration processor configured to execute computer readable instructions stored in a program memory. The hardware input processor determines whether the packet header is to be provided to a processing path coupled to the programmable header alteration processor or to be diverted to a bypass path that bypasses the programmable header alteration processor, and the packet header is provided to the processing path or to the bypass path based on the determination. The packet header is selectively i) processed by the programmable header alteration processor when the packet header is provided to the processing path and ii) not processed by the programmable header alteration processor when the packet header is provided to the bypass path.

At least a packet header of a packet received by a network device is provided to a programmable header alteration engine that includes a hardware input processor implemented in hardware and a programmable header alteration processor configured to execute computer readable instructions stored in a program memory. The hardware input processor determines whether the packet header is to be provided to a processing path coupled to the programmable header alteration processor or to be diverted to a bypass path that bypasses the programmable header alteration processor, and the packet header is provided to the processing path or to the bypass path based on the determination. The packet header is selectively i) processed by the programmable header alteration processor when the packet header is provided to the processing path and ii) not processed by the programmable header alteration processor when the packet header is provided to the bypass path.

Embodiments of the present disclosure are directed to protocol state transition and/or resource state transition tracker configured to monitor, e.g., via filters, for certain protocol state transitions/changes or host hardware resource transitions/changes when a host processor in the control plane that performs such monitoring functions is unavailable or overloaded. The filters, in some embodiments, are pre-computed/computed by the host processor and transmitted to the protocol state transition and/or resource state transition tracker. The protocol state transition and/or resource state transition tracker may be used to implement a fast upgrade operation as well as load sharing and or load balancing operation with control plane associated components.

Embodiments of the present disclosure are directed to protocol state transition and/or resource state transition tracker configured to monitor, e.g., via filters, for certain protocol state transitions/changes or host hardware resource transitions/changes when a host processor in the control plane that performs such monitoring functions is unavailable or overloaded. The filters, in some embodiments, are pre-computed/computed by the host processor and transmitted to the protocol state transition and/or resource state transition tracker. The protocol state transition and/or resource state transition tracker may be used to implement a fast upgrade operation as well as load sharing and or load balancing operation with control plane associated components.

The present invention relates to a reconfigurable switch forwarding engine parser capable of disabling hardware Trojans. The parser comprises a data preprocessing unit, several cascaded basic processing units and an extraction unit, wherein a key path of a basic processing unit of the first stage extracts and shifts a key bit keyword of a key, and sends a result to a data path of the current stage and a key path of the next stage; basic processing units of other stages carry out keyword extraction and shifting on a key frame and the data frame in sequence; and the extraction unit extracts the key frame and the data frame from a basic processing unit of the last stage, and forwards same to a subsequent packet processing part. The present invention can be widely applied to the design of the switch forwarding engine parser.

The present invention relates to a reconfigurable switch forwarding engine parser capable of disabling hardware Trojans. The parser comprises a data preprocessing unit, several cascaded basic processing units and an extraction unit, wherein a key path of a basic processing unit of the first stage extracts and shifts a key bit keyword of a key, and sends a result to a data path of the current stage and a key path of the next stage; basic processing units of other stages carry out keyword extraction and shifting on a key frame and the data frame in sequence; and the extraction unit extracts the key frame and the data frame from a basic processing unit of the last stage, and forwards same to a subsequent packet processing part. The present invention can be widely applied to the design of the switch forwarding engine parser.

Implementations of this disclosure provide data transmission operations and network interface controllers. An example method performed by a first RDMA network interface controller includes obtaining m data packets from a host memory of a first host; sending the m data packets to a second RDMA network interface controller of a second host; backing up the m data packets to a network interface controller memory integrated into the first RDMA network interface controller; determining that the second RDMA network interface controller does not receive n data packets of the m data packets; and in response, obtaining the n data packets from the m data packets that have been backed up to the network interface controller memory integrated into the first RDMA network interface controller, and retransmitting the n data packets to the second RDMA network interface controller.

Implementations of this disclosure provide data transmission operations and network interface controllers. An example method performed by a first RDMA network interface controller includes obtaining m data packets from a host memory of a first host; sending the m data packets to a second RDMA network interface controller of a second host; backing up the m data packets to a network interface controller memory integrated into the first RDMA network interface controller; determining that the second RDMA network interface controller does not receive n data packets of the m data packets; and in response, obtaining the n data packets from the m data packets that have been backed up to the network interface controller memory integrated into the first RDMA network interface controller, and retransmitting the n data packets to the second RDMA network interface controller.

A method and system of a low-latency FPGA framework based on reliable UDP and TCP re-assembly middleware is disclosed. The need for low-latency communication in digital systems has increased drastically. The disclosed FPGA framework enables low-latency communication as a hybrid framework that supports both UDP & TCP communication. As known in art, TCP provides error checking support hence making TCP more reliable as compared to UDP, while UDP is faster but not reliable. Hence the disclosed low-latency FPGA framework latency utilizes the advantage of both UDP and TCP by utilizing UDP for its speed, while switching to TCP in case of a missing sequence in UDP. Further, the disclosed system proposes a TCP re-assembly middleware architecture for processing TCP with a lower-latency, wherein the TCP re-assembly middleware is an independent middleware that is a modular and a plug-play independent middleware.