In a solid-state imaging element equipped with per-column ADCs, noise is reduced. A test signal source generates a test signal of a predetermined level. An analog-to-digital converter increases/decreases an analog signal according to an analog gain selected from among a plurality of analog gains, and converts the increased/decreased analog signal to a digital signal. An input switching section inputs, as the analog signal, either a test signal or a pixel signal to the analog-to-digital converter. A correction value calculation section obtains, on the basis of the test signal and the digital signal, a correction value for correcting an error in the selected analog gain, and outputs the correction value. A correction section corrects the digital signal according to the outputted correction value.

In a solid-state imaging element equipped with per-column ADCs, noise is reduced. A test signal source generates a test signal of a predetermined level. An analog-to-digital converter increases/decreases an analog signal according to an analog gain selected from among a plurality of analog gains, and converts the increased/decreased analog signal to a digital signal. An input switching section inputs, as the analog signal, either a test signal or a pixel signal to the analog-to-digital converter. A correction value calculation section obtains, on the basis of the test signal and the digital signal, a correction value for correcting an error in the selected analog gain, and outputs the correction value. A correction section corrects the digital signal according to the outputted correction value.

An image sensor may include an array of image pixels. The array of image pixel may be coupled to control circuitry and readout circuitry. One or more image pixels in the array may each include a photodiode and a floating diffusion region. The floating diffusion region may be coupled to a charge storage structure for a low conversion gain configuration and can be coupled to a charge storage structure for a medium conversion gain configuration. The medium conversion gain charge storage structure may be activated when transferring photodiode charge to the floating diffusion region for a high conversion gain configuration. The control circuitry may control each pixel to perform a high conversion gain readout operation, a medium conversion gain readout operation, and a low conversion gain readout operation. If desired, the medium conversion gain readout operation may be omitted.

An image sensor may include an array of image pixels. The array of image pixel may be coupled to control circuitry and readout circuitry. One or more image pixels in the array may each include a photodiode and a floating diffusion region. The floating diffusion region may be coupled to a charge storage structure for a low conversion gain configuration and can be coupled to a charge storage structure for a medium conversion gain configuration. The medium conversion gain charge storage structure may be activated when transferring photodiode charge to the floating diffusion region for a high conversion gain configuration. The control circuitry may control each pixel to perform a high conversion gain readout operation, a medium conversion gain readout operation, and a low conversion gain readout operation. If desired, the medium conversion gain readout operation may be omitted.

Techniques are described for efficient high-resolution output of an image captured using a high-pixel-count image sensor based on pixel binning followed by luminance-guided umsampling. For example, an image sensor array is configured according to a red-green-blue-luminance (RGBL) CFA pattern, such that at least 50-percent of the imaging pixels of the array are luminance (L) pixels. Pixel binning is used during readout of the array to concurrently generate a downsampled RGB capture frame and a downsampled L capture frame. Following the readout, the L capture frame is upsampled (e.g., by upscaling and interpolation) to generate an L guide frame with 100-percent luminance density. An upsampled RGB frame can then be generated by interpolating the RGB capture frame based both on known neighboring RGB information (e.g., from the RGB capture frame and previously interpolated information), as adjusted based on local luminance information from the L guide frame.

Techniques are described for efficient high-resolution output of an image captured using a high-pixel-count image sensor based on pixel binning followed by luminance-guided umsampling. For example, an image sensor array is configured according to a red-green-blue-luminance (RGBL) CFA pattern, such that at least 50-percent of the imaging pixels of the array are luminance (L) pixels. Pixel binning is used during readout of the array to concurrently generate a downsampled RGB capture frame and a downsampled L capture frame. Following the readout, the L capture frame is upsampled (e.g., by upscaling and interpolation) to generate an L guide frame with 100-percent luminance density. An upsampled RGB frame can then be generated by interpolating the RGB capture frame based both on known neighboring RGB information (e.g., from the RGB capture frame and previously interpolated information), as adjusted based on local luminance information from the L guide frame.

A light sensor is disclosed. The light sensor comprises a first pixel and a second pixel. The light sensor comprises measurement circuitry. The first pixel is configured to accumulate a first charge and the second pixel is configured to accumulate a second charge when the light sensor is exposed to light. The first pixel is configured to trigger the measurement circuitry to measure the second charge when the first charge reaches a threshold capacity of the first pixel. Also disclosed is an active pixel sensor comprising the light sensor, an image sensor and a device incorporating the light sensor.

An imaging device includes a varifocal lens and an imaging sensor which outputs a signal corresponding to light. The imaging sensor includes a photoelectric conversion unit which converts light into an electric charge, electric charge reading regions, transfer control electrodes, a gate control circuit which sequentially applies control signals to the transfer control electrodes to correspond to the position of the focal point of the varifocal lens, and a reading circuit which outputs a signal corresponding to the amount of the electric charge transferred to the electric charge reading regions. The gate control circuit repeats an operation of outputting each of the control signals when the position of the focal point is located in the focal ranges during a frame period.

An infrared processing system includes a first thermal image generating unit, an object extracting unit, a second thermal image generating unit, and an object temperature calculating unit. The first thermal image generating unit generates, using a first temperature correction value, a first thermal image based on the output signal of the image sensor. The object extracting unit extracts the object from the first thermal image. The second thermal image generating unit generates, using a second temperature correction value corresponding to the object that has been extracted by the object extracting unit, a second thermal image based on the output signal of the image sensor. The object temperature calculating unit calculates, based on the second thermal image that has been generated by the second thermal image generating unit, a temperature of the object that has been extracted by the object extracting unit.

In one example, an apparatus comprises: a memory to store input data and weights, the input data comprising groups of data elements, each group being associated with a channel of channels, the weights comprising weight tensors, each weight tensor being associated with a channel of the channels; a data sparsity map generation circuit configured to generate, based on the input data, a channel sparsity map and a spatial sparsity map, the channel sparsity map indicating channels associated with first weights tensors to be selected, the spatial sparsity map indicating spatial locations of first data elements; a gating circuit configured to: fetch, based on the channel sparsity map and the sparsity map, the first weights tensors and the first data elements from the memory; and a processing circuit configured to perform neural network computations on the first data elements and the first weights tensors to generate a processing result.