In a solid-state imaging element that measures a distance, miniaturization of pixels is facilitated. The solid-state imaging element includes a pixel array unit and a photon number detection unit. In the solid-state imaging element including the pixel array unit and the photon number detection unit, the pixel array unit is provided with a plurality of pixels that generates a predetermined analog signal depending on incidence of a photon and a signal line to which the plurality of pixels is connected in common. Furthermore, in the solid-state imaging element, the photon number detection unit detects the number of photons incident, on the basis of the analog signal transmitted via the signal line.

A depth sensor for measuring a distance to an object and an image signal processor configured to change a binning mode based on ambient light are provided. A method for operating a depth sensor for measuring a distance to an object includes outputting a pixel signal from at least one depth pixel included in a pixel array, generating ambient light information based on an intensity of ambient light outside the depth sensor, the intensity of the ambient light being measured using the pixel signal, and setting a binning mode of the depth sensor to an analog binning mode or a digital binning mode based on the ambient light parameter value.

A hybrid ferroelectric-metal-oxide-semiconductor field effect transistor (Fe-MOSFET) device is described, such as for incorporation into in-pixel circuitry of an imaging pixel array to provide both reset and dual conversion gain features. The Fe-MOSFET includes source and drain regions implanted in a semiconductor substrate and separated by a channel region. The source region can be the floating diffusion region of a photosensor. A gate structure is deposited on the substrate directly above at least the channel region and an isolating layer is formed on the surface of the substrate to electrically isolate the gate structure from at least the channel region. The isolating layer is split into a Fe segment of ferroelectric material that can be written to different polarization states for conversion gain control, and a dielectric segment that can be used for current channel formation in the channel region.

An electronic apparatus includes an imaging element having a plurality of image capture regions, each of the image capture regions having a plurality of pixels for generating an image signal; a setting unit that sets different image capture conditions for the plurality of image capture regions; and a control unit that corrects a portion of an image signal of a photographic subject captured under first image capture conditions in an image capture region among the plurality of image capture regions so that it is as if the portion of the image signal was captured under second image capture conditions.

A method for sampling data from pixels of an event vision sensor is disclosed. The method comprises receiving, with a selection circuit, an activation signal from an active pixel of the plurality of pixels of the line, generating, with the selection circuit, an acknowledge signal in response to receiving the activation signal, and sending the acknowledge signal to the plurality of pixels of the line, wherein each pixel of the line is configured to generate a request-reading signal when that pixel is active when receiving the acknowledge signal. The method also includes electrically coupling a control circuit to a pixel having a largest distance to the selection circuit among the plurality of pixels of the line, receiving, with the control circuit, the acknowledge signal from the selection circuit, generating, with the control circuit, a process-reading signal in response to receiving the acknowledge signal, and resetting the selection circuit and the plurality of pixels of the line after receiving the process-reading signal.

A method for sampling data from pixels of an event vision sensor is disclosed. The method comprises receiving, with a selection circuit, an activation signal from an active pixel of the plurality of pixels of the line, generating, with the selection circuit, an acknowledge signal in response to receiving the activation signal, and sending the acknowledge signal to the plurality of pixels of the line, wherein each pixel of the line is configured to generate a request-reading signal when that pixel is active when receiving the acknowledge signal. The method also includes electrically coupling a control circuit to a pixel having a largest distance to the selection circuit among the plurality of pixels of the line, receiving, with the control circuit, the acknowledge signal from the selection circuit, generating, with the control circuit, a process-reading signal in response to receiving the acknowledge signal, and resetting the selection circuit and the plurality of pixels of the line after receiving the process-reading signal.

The present technology relates to a display control device, a display control method, and a program enabling images to be checked in real time.

A display control device includes: a receiving unit that receives small volume data that is information on current imaging by an artificial satellite; and a control unit that displays a live view image based on the small volume data on a display unit, wherein the receiving unit receives a satellite image corresponding to the live view image as large volume data at a timing different from that of the small volume data. The present technology can be applied to, for example, a satellite image processing system that processes satellite images captured by artificial satellites.

An imaging device that smoothly transfers electric charges from a photoelectric converter to a transfer destination is provided. This imaging device includes: a semiconductor layer; a photoelectric converter that generates electric charges corresponding to a received light amount; and a transfer section that includes a first trench gate and a second trench gate and transfers the electric charges from the photoelectric converter to a single transfer destination via the first trench gate and the second trench gate, the first trench gate and the second trench gate each extending from the front surface to the back surface of the semiconductor layer into the photoelectric converter. The first trench gate has a first length from the front surface to the photoelectric converter, and the second trench gate has a second length from the front surface to the photoelectric converter, the second length being shorter than the first length.

Systems and techniques are described for imaging. An imaging system includes an image sensor with a plurality of photodetectors, grouped into a first group of photodetectors and a second group of photodetectors. The imaging system can reset its image sensor. The imaging system exposes its image sensor to light from a scene. The plurality of photodetectors convert the light into charge. The imaging system stores analog photodetector signals corresponding to the charge from each the photodetectors. The imaging system reads first digital pixel data from a first subset of the analog photodetector signals corresponding to the first group of photodetectors without reading second digital pixel data from a second subset of the analog photodetector signals corresponding to the second group of photodetectors. The imaging system generates an image of the scene using the first digital pixel data.

An imaging device includes a pixel array including pixel circuits arranged into rows and columns. Each bitline of a plurality of bitlines is coupled to a respective column of pixel circuits of the pixel array. The plurality of bitlines is grouped into pairs of bitlines. A plurality of binning circuits is coupled to the plurality of bitlines. Each binning circuit is coupled to a respective pair of bitlines and is responsive to a multi-mode select signal. Each binning circuit is configured to output a binned signal responsive to the first and second bitlines of the respective bitline pair in a first mode. Each binning circuit is configured to output a first signal from a first bitline of the respective bitline pair in a second mode. Each binning circuit is configured to output a second signal from the second bitline of the respective bitline pair in a third mode.