A module substrate antenna includes: a laminate in which a plurality of ferrite layers are stacked; antennal coils provided on surfaces of the respective ferrite layers; a connection pad connected to an external circuit; and a lead wire provided between the laminate and the connection pad. In the laminate, the antenna coils are two types of the antenna coils, and the two types of the antenna coils are alternately stacked.

A device source wafer includes a wafer substrate, devices formed on or in the wafer substrate at a location on the wafer substrate, and test structures disposed on the wafer substrate connected to some but not all of the devices. The devices include a first device disposed at a first location and a second device disposed at a second different location on the wafer substrate. The test structures include at least a first test structure connected to the first device and a second test structure connected to the second device. The first test structure is adapted to measuring a characteristic of the first device and the second test structure is adapted to measuring the characteristic of the second device. An estimated characteristic of unmeasured devices is derived from the first and second device locations and measured characteristics and the device is selected based on the estimated characteristic.

A processor substrate includes: an electrically insulating material having a first main side and a second main side opposite the first main side; a plurality of electrically conductive structures embedded in the electrically insulating material and configured to provide an electrical interface at the first main side of the electrically insulating material and to provide electrical connections from the electrical interface to the second main side of the electrically insulating material; and a power device module embedded in the electrically insulating material and configured to convert a voltage provided at the second main side of the electrically insulating material and which exceeds a voltage limit of the processor substrate to a voltage that is below the voltage limit of the processor substrate. An electronic system that includes the processor substrate is also described.

A printed circuit board (PCB) comprises a blind via and a discrete component vertically embedded within the blind via.

Embodiments may include inductors with embedded magnetic cores and methods of making such inductors. In an embodiment, an integrated circuit package may include an integrated circuit die with a multi-phase voltage regulator electrically coupled to the integrated circuit die. In such embodiments, the multi-phase voltage regulator may include a substrate core and a plurality of inductors. The inductors may include a conductive through-hole disposed through the substrate core and a plugging layer comprising a dielectric material surrounding the conductive through-hole. In an embodiment, a magnetic sheath is formed around the plugging layer. In an embodiment, the magnetic sheath is separated from the plated through hole by the plugging layer. Additionally, a first layer comprising a dielectric material may be disposed over a first surface of the magnetic sheath, and a second layer comprising a dielectric material may be disposed over a second surface of the magnetic sheath.

The disclosure relates to methods for fabricating coreless printed circuit board (PCB) based transformers and/or coreless PCB-based circuits containing one or more coil inductor(s). More specifically, the disclosure relates to methods for fabricating coreless PCB-based transformers and/or inductors having concatenated helix architecture of their primary and secondary windings using layer-by-layer printing of dielectric and conductive patterns.

Apparatus and methods of automatically trimming a PCB-based LC circuit. The apparatus may comprise an interface to a printed circuit board (PCB). The PCB may include a PCB inductor and a PCB capacitor to form an LC circuit. The LC circuit may have an LC circuit frequency. The apparatus may comprise a variable capacitor communicatively coupled to the interface and configured to adjust an effective capacitance of the LC circuit.

An apparatus is disclosed for transferring a pattern of a composition containing particles of an electrically conductive material and a thermally activated adhesive from a surface of a flexible web to a surface of a substrate. The apparatus comprises: respective drive mechanisms for advancing the web and the substrate to a nip through which the web and the substrate pass at the same time and where a pressure roller acts to press the surfaces of the web and the substrate against one another, a heating station for heating at least one of the web and the substrate prior to, or during, passage through the nip, to a temperature at which the adhesive in the composition is activated, a cooling station for cooling the web after passage through the nip, and a separating device for peeling the web away from the substrate after passage through the cooling station, to leave the pattern of composition adhered to the surface of the substrate.

A component carrier with an electrically insulating layer structure has opposed main surfaces, a through-hole, and an electrically conductive bridge structure connecting opposing sidewalls delimiting the through-hole. The sidewalls have a first tapering portion extending from a first main surface and a second tapering portion extending from a second main surface. A first demarcation surface faces the first main surface and a second demarcation surface faces the second main surface. A central bridge plane extends parallel to the first main surface and the second main surface and is at a vertical center between a lowermost point of the first demarcation surface and an uppermost point of the second demarcation surface. A first intersection point is between the central bridge plane and one of the sidewalls delimiting the through hole. A length of a shortest distance from the first intersection point to the first demarcation surface is at least 8 μm.

Embodiments of the disclosure relate to apparatuses for enhanced thermal management of an inductor assembly using functionally-graded thermal vias for heat flow control in the windings of the inductor. In one embodiment, a PCB for an inductor assembly includes a top surface and a bottom surface. Two or more electrically-conductive layers are embedded within the PCB and stacked vertically between the top surface and the bottom surface. The two or more electrically-conductive layers are electrically connected to form an inductor winding. A plurality of thermal vias thermally connects each of the two or more electrically-conductive layers to a cold plate thermally connected to the bottom surface. A number of thermal vias thermally connecting each electrically-conductive layer to the cold plate is directly proportional to a predetermined rate of heat dissipation from the electrically-conductive layer.