Patent classifications
H05K3/0005
FIBER WEAVE SKEW ASSESSMENT FOR PRINTED CIRCUIT BOARDS
In one embodiment, a method includes inspecting a layer of a printed circuit board through an inspection window comprising an opening formed in one or more other layers of the printed circuit board and identifying a location of a trace aligned with the inspection window, relative to a marker in a fiber bundle of a fiber weave to assess fiber weave skew.
TRACE LENGTH ON PRINTED CIRCUIT BOARD (PCB) BASED ON INPUT/OUTPUT (I/O) OPERATING SPEED
A wireline communications system is described. The wireline communications system includes a printed circuit board (PCB). The wireline communications system also includes a system on chip (SoC) die on the PCB. The wireline communications system further includes an external memory device coupled to a memory interface of the SoC die. The external memory device is coupled to the memory interface of the SoC die through a PCB trace. A length of the PCB trace is configured according to an operating speed of the memory interface.
Controlled-impedance printed-circuit board (PCB) design with stack-up re-mapping
A controlled-impedance printed circuit board (PCB) design program allows interactive movement of features from one of the vertically-stacked layers of the design to another layer in a graphical interface. The movement either moves a region of a layer of the PCB design, or moves an entire layer in a layer-swapping operation. The program computes modified widths of circuit traces of the first layer of the controlled-impedance printed circuit board design according to an impedance control value of the controlled-impedance printed circuit board design and according to a new position of the circuit traces caused by a movement of the features of the first layer to the second layer. The program also checks for violation of reference plane requirements for critical signals and warns the designer if such a violation is present.
Array type discrete decoupling under BGA grid
Various exemplary embodiments relate to a printed circuit board (PCB) for electrically connecting a discrete array component including a pattern formed on the PCB which is a merger of a set of via pads and a discrete array component; wherein the pattern is generated by a pin mapping between the discrete array component and a via grid array on the PCB; and wherein the pattern is formed of a metal etched during a manufacturing process of the PCB.
PCBA INSPECTION METHOD AND SYSTEM BASED ON 3D AOI AND AXI
The present disclosure provides a PCBA detection method and a system based on 3D AOI and AXI. The method includes: preconfiguring graphical data in a part physical database; obtaining CAD data related to a PCB based on design data input from PCB design software; converting the generated CAD data, and generating 3D basic graphical data to generate a 3D physical model; extracting BOM information from the design data, searching the part physical database for matched graphical data based on the BOM information, if the matched graphical data is found, generating a 3D physical model based on the graphical data; if the matched graphical data is not found, generating corresponding image data based on obtained created data, to generate a 3D physical model; and generating standard 3D detection prototype data, outputting the standard 3D detection prototype data to 3D AOI and AXI for detection.
POWER NETWORK DC INTEGRITY CHECKS OF PCBS
A system and method for integrity analysis of a printed circuit board comprises a processor and a first set of instructions executable on the processor configured to use a two-dimensional mesh for the analysis of the printed circuit board to reduce the number of elements in a mesh representing the printed circuit board. A second set of instructions are executable on the processor are configured to use a resistive line to replace all vias and a third set of instructions are executable on the processor configured to approximate the contours of shapes in the printed circuit board to further reduce the number of elements.
Pixelized thermal conductivity determination for printed circuit boards
Various aspects of the disclosed technology relate to pixel-based thermal conductivity determination. A pixelized representation is created for a conductor layer of a printed circuit board. The pixelized representation is analyzed to identify conductor paths in a direction. Based on the conductor paths, the conductor pixels separated into net pixels and isolated pixels. An effective thermal conductivity property value in the direction is then computed for a section or a whole of the conductor layer based on the number of the isolated pixels, the number of the net pixels and the number of total pixels in the section or the whole of the conductor layer.
PRINTED CIRCUIT BOARD STRUCTURE, AND WIRING METHOD THEREFOR
A printed circuit board structure and a wiring method therefor are disclosed. The printed circuit board structure comprises a first wiring channel formed inside the printed circuit board for transmitting a circuit signal; a pin, connected to the first wiring channel for connecting a chip to the printed circuit board; the pin comprising an unused pin and a used pin, the used pin comprising a peripheral pin and an internal pin; wherein the printed circuit board further comprises a second wiring channel, the second wiring channel leads out the internal pin by means of covering at least a portion of the unused pin. By means of using a printed circuit board structure and a wiring method to configure pins of the printed circuit board, the number of printed circuit board layers is reduced, and the current carrying capacity is enhanced.
Printed circuit board connection for integrated circuits using two routing layers
Methods, systems, and apparatus, including printed circuit boards (PCBs) with trace routing topologies are disclosed. In one aspect, a PCB includes an external layer that includes multiple integrated circuit (IC) installation regions that are each configured to receive an IC, a first trace routing layer having a first conductive trace that is routed along a first path from a first IC installation region to a second IC installation region, a second trace routing layer having a second conductive trace that is routed along a second path from the first IC installation region to the second IC installation region, a first via region having one or more first vias that extend from the first trace routing layer to the second trace routing layer, and a second via region having one or more second vias that extend from the first trace routing layer to the second trace routing layer.
MICROCAPSULE, SHEET MATERIAL, CIRCUIT BOARD, METHOD FOR MANUFACTURING CIRCUIT BOARD, AND COMPUTER READABLE STORAGE MEDIUM
A microcapsule includes a shell including a conducting component, and a thermally expandable component contained in the shell and having a property of expanding by heating. The shell is deformable in accordance with expansion of the thermally expandable component when the thermally expandable component is heated.