An electronic breadboard system may include a computing device including a display screen. The display screen has a first portion to display an electronic circuit model and a second portion directly adjacent to the first portion. The electronic breadboard system also includes a translucent breadboard on the second portion of the display screen. The translucent breadboard includes a translucent face plate having a rectangular grid of openings exposing a plurality of contacts. The plurality of contacts are arranged lengthwise along each row of the rectangular grid of openings and orthogonal to a transparent back plate coupling the plurality of contacts to the translucent face plate. The electronic breadboard system includes a graphics controller. The graphics controller may illuminate a row opening and/or a column opening of the translucent breadboard to direct placement of electrical components of a computer model in response to user interaction with the electronic circuit model.

A printed circuit board (PCB) panelization method and a PCB panelization system are disclosed herein. The PCB panelization method comprises the following steps: S1, reading daughterboard information of purchase orders, wherein the daughterboard information comprises respective areas, delivery quantities and attributes of daughterboards; S2, performing comparison of the daughterboard information, screening for daughterboards having attributes that are the same, and establishing a panelization rule database; S3, selecting panels (PNLs) satisfying requirements according to panelization requirements; S4, selecting, from the daughterboards having the same attributes as the selected panels, daughterboards to be panelized together for the selected panels, and arranging a graphical layout for a panelization of the selected panels. The system comprises: a reading module-used for reading the daughterboard information of the purchase orders; the panelization rule database for storing the information of the screened daughterboards having the same attributes; a panel selecting module used for selecting the panel satisfying the requirements according to the panelization requirements; and a panelization engine calculation module used for selecting the daughterboards in order from large to small, determining whether the daughterboards can be panelized together, determining whether the arrangement of the layout for the panelization is successful, determining the daughterboards to be panelized together finally, and arranging the layout for the panelization.

Methods, systems, and apparatus, including printed circuit boards (PCBs) with trace routing topologies are disclosed. In one aspect, a PCB includes an external layer that includes multiple integrated circuit (IC) installation regions that are each configured to receive an IC, a first trace routing layer having a first conductive trace that is routed along a first path from a first IC installation region to a second IC installation region, a second trace routing layer having a second conductive trace that is routed along a second path from the first IC installation region to the second IC installation region, a first via region having one or more first vias that extend from the first trace routing layer to the second trace routing layer, and a second via region having one or more second vias that extend from the first trace routing layer to the second trace routing layer.

A system and method to automatically determine power plane shape in a printed circuit board (PCB) involve obtaining inputs. The inputs include a size and shape of the PCB, a set of sources, and a set of sinks associated with a power plane. The method also includes determining a center of charge (CoC) as a center of largest current density for the set of sources and the set of sinks, and creating a sub-shape corresponding with a path from each source of the set of sources and from each sink of the set of sinks to the CoC. The creating the sub-shape includes determining a width of a conductor in the path corresponding with each of the sub-shapes. The sub-shapes created for the set of sources and the set of sinks are combined as the power plane shape.

A method for generating an electronic component representation for use in a printed circuit board design tool includes providing a plurality of training datasheets, learning, during off-line symbol processing, to identify component symbols based on the training datasheets, and storing in memory the learned identified symbol characteristics. Also included is learning, during off-line footprint processing, to identify component footprints based on the training datasheets, and storing the learned identified footprint characteristics in memory. Once off-line training has been performed, a user provides a selected component datasheet containing a component to use in the printed circuit board design tool, and on-line processing extracts a component symbol and footprint of the selected component based on the learned symbol and learned footprint characteristics. The extracted symbol and footprint are merged to generate a completed component corresponding to the selected component, which is then provided to the printed circuit board design tool for use in the design and layout of the PCB.

A method includes: providing a first layout of a first layer over a substrate, the first layer having at least one metal pattern, and generating a second layout by placing a cut mask at a first position relative to the substrate to remove material from a first region of the at least one metal pattern to provide a first metal pattern and placing the cut mask at a second position relative to the first layer over the substrate to remove material from a second region of the at least one metal pattern to provide a second metal pattern.

An information processing apparatus includes a memory, and a processor coupled to the memory and configured to receive a designation of a progression degree in which a circuit pattern displayed on a two-dimensional model of a printed circuit board is traced from a start point to an end point of the circuit pattern, display, on the two-dimensional model, the circuit pattern from the start point to a point corresponding to the progression degree on a three-dimensional model of the printed circuit board based on a setting of the start point and the end point of the circuit pattern, and display the circuit pattern of the two-dimensional model to distinguish a first pattern to form a part of the circuit pattern and a second pattern to form a part of the circuit pattern, the first pattern and the second pattern having portions overlapping each other.

A printed circuit board having a substrate layer, at least one electrically conductive trace disposed on the substrate layer, and a solder mask layer disposed over the substrate layer and the electrically conductive trace, wherein the solder mask later includes a void region over at least a portion of the electrically conductive trace. Also, a method of optimizing printed circuit board designing including selecting printed circuit board data comprising at least a solder mask layer area, varying the solder mask layer area, determining an insertion loss value for each varied solder mask layer area, comparing the insertion loss values for each varied solder mask layer area, and selecting a solder mask layer area based on the comparing.

A controlled-impedance printed circuit board (PCB) design program allows interactive movement of features from one of the vertically-stacked layers of the design to another layer in a graphical interface. The movement either moves a region of a layer of the PCB design, or moves an entire layer in a layer-swapping operation. The program computes modified widths of circuit traces of the first layer of the controlled-impedance printed circuit board design according to an impedance control value of the controlled-impedance printed circuit board design and according to a new position of the circuit traces caused by a movement of the features of the first layer to the second layer. The program also checks for violation of reference plane requirements for critical signals and warns the designer if such a violation is present.

A spatial model of a printed circuit board assembly is generated based on an input file. The spatial model is used to determine a spatial feature not directly specified in the input file. A manufacturing parameter is determined based at least in part on the determined spatial feature. A proposal to manufacture the printed circuit board assembly is generated programmatically based at least in part on the determined manufacturing parameter.