A design method for displaying a DRC in a classification manner in a PCB design is provided. The design method includes: acquiring layer information contained in a current design, adding the acquired layer information to a DRC Layer menu in a pop up window, acquiring a DRC Type contained in the current design and adding the processed DRC Type to a DRC Type menu in the pop up window after processing the acquired DRC Type; creating an updating function, to update a DRC Type menu list in response to an input action of a user; acquiring an attribute of each item in a DRC Layer menu list and the DRC Type menu list, and inserting the acquired attribute into the updated DRC Layer menu list and the updated DRC Type menu list, to form a feature parameter list.

A method includes, receiving a layout design of at least part of an electronic module, the design specifying at least (i) an electronic device coupled to at least a substrate, and (ii) an electrical trace that is connected to the electronic device and has a designed route. A digital input, which represents at least part of an actual electronic module that was manufactured in accordance with the layout design but without at least a portion of the electrical trace, is received. An error in coupling the electronic device to the substrate, relative to the layout design, is estimated based on the digital input. An actual route that corrects the estimated error, is calculated for at least the portion of the electrical trace. At least the portion of the electrical trace is formed on the substrate of the actual electronic module, along the actual route instead of the designed route.

An assembly method and device for a circuit structural member, and a circuit structural member. The assembly method comprises: measuring a depth and path of a channel between at least one chip and a printed circuit board (PCB), the at least one chip being arranged on the PCB; determining a thickness and path of a heat dissipation reinforcement material according to the depth and path of the channel between the at least one chip and the PCB and a predetermined heat dissipation parameter, so as to configure a dispensing parameter and a dispensing path; coating the heat dissipation reinforcement material in the channel between the at least one chip and the PCB according to the dispensing parameter and dispensing path; and heating the heat dissipation reinforcement material to a first predetermined temperature, such that the heat dissipation reinforcement material permeates into the chip and the PCB.

A wireline communications system is described. The wireline communications system includes a printed circuit board (PCB). The wireline communications system also includes a system on chip (SoC) die on the PCB. The wireline communications system further includes an external memory device coupled to a memory interface of the SoC die. The external memory device is coupled to the memory interface of the SoC die through a PCB trace. A length of the PCB trace is configured according to an operating speed of the memory interface.

A method is provided that includes inspecting a layer of a printed circuit board through an inspection window comprising an opening formed in one or more other layers of the printed circuit board and identifying a location of a trace aligned with the inspection window, relative to a marker in a fiber bundle of a fiber weave to assess fiber weave skew.

A system to access one or more user profiles that govern one or more vehicle functions. The system cooperates with a processor and verification module which are adapted to verify, using one or more of biometric information, gesture recognition, facial recognition and device identification information, that a user has authority to access the one or more user profiles, where the one or more profiles are stored in one or more of a vehicle, a cloud and a communications device. An edit module is further provided and adapted to allow the user to make one or more edits to the one or more user profiles.

An object here is to provide a control device which can be reduced in size, weight and cost while being able to prevent unauthorized access. The control device includes: a microcontroller having a storage device, a processor, a package in which the storage device and the processor are accommodated, and multiple communication electrodes provided on a bottom surface of the package; and a wiring board having wiring layers comprised of a front surface layer, an intermediate layer and a rear surface layer, each having a wiring pattern formed therein, insulating members for insulating the respective wiring layers from each other; interlayer connection portions each making an electrical connection between the wiring patterns in different ones of the wiring layers; multiple electrode pads formed n the front surface layer; and communication-dedicated interlayer connection portions which are electrically connected to the respective electrode pads, and which are each externally exposed.

A stencil-avoidance design method, a stencil-avoidance design device, an electronic device, and a non-transitory storage medium are provided. The method includes: obtaining a plurality of first regions and a plurality of first stencil aperture regions; determining whether a shortest distance between a selected first region of the plurality of first regions and a selected first stencil aperture region of the plurality of first stencil aperture regions is within a preset threshold range; further obtaining a second region and a second stencil aperture region if the shortest distance is within the preset threshold range, and then obtaining a third region; performing a collision step if a collision test is required, and obtaining a final stencil aperture region. The above method can improve the efficiency, accuracy, coverage, and comprehensiveness of the stencil avoidance design.

A method includes, receiving a layout design of at least part of an electronic module, the design specifying at least (i) an electronic device coupled to at least a substrate, and (ii) an electrical trace that is connected to the electronic device and has a designed route. A digital input, which represents at least part of an actual electronic module that was manufactured in accordance with the layout design but without at least a portion of the electrical trace, is received. An error in coupling the electronic device to the substrate, relative to the layout design, is estimated based on the digital input. An actual route that corrects the estimated error, is calculated for at least the portion of the electrical trace. At least the portion of the electrical trace is formed on the substrate of the actual electronic module, along the actual route instead of the designed route.

A component carrier includes a stack having a first electrically insulating layer structure and a first electrically conductive layer structure arranged on the first electrically insulating layer structure. The first electrically insulating layer structure has at least one first covered portion, which is covered by the first electrically conductive layer structure, and at least one first non-covered portion, which is not covered by the first electrically conductive layer structure. The first electrically insulating layer structure defines a recess at the at least one first non-covered portion.