A method for manufacturing a circuit board including the following steps: providing a flexible double-sided metal-clad laminate including a first metal foil, a flexible dielectric layer, and a second metal foil. A carrier is attached to the second metal foil. A first wiring layer including a first wiring region and a second wiring region is formed by the first metal foil. The first wiring region includes a first connecting pad, and the second wiring region includes a connecting pad. A plurality of rigid dielectric blocks surrounded to form an interval and a first groove exposing the first connecting pad is pressed on the flexible dielectric layer to form a rigid dielectric layer. An electronic component is fixed the first groove. The carrier is removed. The intermediate structure is bent along the interval and pressed. A second wiring layer is formed by the second metal foil.

A substrate is manufactured by drilling a chip containing groove in a composite inner layer circuit structure, having a component connecting end of a circuit layer protruding from a mounting side wall in the chip containing groove, mounting a chip component in the chip containing groove, and connecting the surface bonding pad to the component connecting end. The chip component in the present invention penetrates at least two circuit layers, and the surface bonding pad is bonded to the component connecting end of the circuit layer directly, reducing the occupied area of the chip component in each one of the circuit layers, and increasing the area for circuit disposing and the possible amount of chip components that may be mounted in the substrate.

A substrate is manufactured by drilling a chip containing groove in a composite inner layer circuit structure, having a component connecting end of a circuit layer protruding from a mounting side wall in the chip containing groove, mounting a chip component in the chip containing groove, and connecting the surface bonding pad to the component connecting end. The chip component in the present invention penetrates at least two circuit layers, and the surface bonding pad is bonded to the component connecting end of the circuit layer directly, reducing the occupied area of the chip component in each one of the circuit layers, and increasing the area for circuit disposing and the possible amount of chip components that may be mounted in the substrate.

An embodiment of the present invention provides a copper foil which comprises a copper layer and an anticorrosive film placed on the copper layer, and has a Young's modulus of 3800 to 4600 kgf/mm.sup.2 and a modulus bias factor (MBF) less than 0.12, wherein the modulus bias factor (MBF) is obtained by formula 1 below.
MBF=(maximum Young's modulus−minimum Young's modulus)/(average Young's modulus)  [Formula 1]

A electronic component including a first protective layer covering the substrate and the conductive tract, a second protective layer covering at least a portion of the first protective layer, wherein the second protective layer includes Parylene, and a third protective layer covering at least a portion of the second protective layer.

A method for manufacturing a circuit board including the following steps: providing a flexible double-sided metal-clad laminate including a first metal foil, a flexible dielectric layer, and a second metal foil. A carrier is attached to the second metal foil. A first wiring layer including a first wiring region and a second wiring region is formed by the first metal foil. The first wiring region includes a first connecting pad, and the second wiring region includes a connecting pad. A plurality of rigid dielectric blocks surrounded to form an interval and a first groove exposing the first connecting pad is pressed on the flexible dielectric layer to form a rigid dielectric layer. An electronic component is fixed the first groove. The carrier is removed. The intermediate structure is bent along the interval and pressed. A second wiring layer is formed by the second metal foil.

A method for manufacturing a circuit board including the following steps: providing a flexible double-sided metal-clad laminate including a first metal foil, a flexible dielectric layer, and a second metal foil. A carrier is attached to the second metal foil. A first wiring layer including a first wiring region and a second wiring region is formed by the first metal foil. The first wiring region includes a first connecting pad, and the second wiring region includes a connecting pad. A plurality of rigid dielectric blocks surrounded to form an interval and a first groove exposing the first connecting pad is pressed on the flexible dielectric layer to form a rigid dielectric layer. An electronic component is fixed the first groove. The carrier is removed. The intermediate structure is bent along the interval and pressed. A second wiring layer is formed by the second metal foil.

A method for manufacturing a circuit board with narrow conductive traces and narrow spaces between traces includes a base layer and two first wiring layers disposed on opposite surfaces of the base layer. Each first wiring layer includes a first bottom wiring and a first electroplated copper wiring. The first bottom wiring is formed on the base layer. The first bottom wiring includes a first end facing the base layer, a second end opposite to the first end, and a first sidewall connecting the first end and the second end. The first electroplated copper wiring covers the second end and the first sidewall of the first bottom wiring.

Disclosed herein are laser scanning systems and methods of their use. In some embodiments, laser scanning systems can be used to ablatively or non-ablatively scan a surface of a material. Some embodiments include methods of scanning a multi-layer structure. Some embodiments include translating a focus-adjust optical system so as to vary laser beam diameter. Some embodiments make use of a 20-bit laser scanning system.

Disclosed herein are laser scanning systems and methods of their use. In some embodiments, laser scanning systems can be used to ablatively or non-ablatively scan a surface of a material. Some embodiments include methods of scanning a multi-layer structure. Some embodiments include translating a focus-adjust optical system so as to vary laser beam diameter. Some embodiments make use of a 20-bit laser scanning system.