A bonding structure includes a first layer of first alloy component disposed on a substrate and a first layer of a second alloy component disposed on the first alloy component. The second alloy component has a lower melting temperature than the first alloy component. A second layer of the first alloy component is disposed on the first layer of the second alloy component and a second layer of the second alloy component is disposed on the second layer of the first alloy component.

A bonding structure includes a first layer of first alloy component disposed on a substrate and a first layer of a second alloy component disposed on the first alloy component. The second alloy component has a lower melting temperature than the first alloy component. A second layer of the first alloy component is disposed on the first layer of the second alloy component and a second layer of the second alloy component is disposed on the second layer of the first alloy component.

A method for manufacturing an electronic device is disclosed. The electronic device has a first region and a transparent region. The method includes the steps of providing a substrate, forming an electric circuit layer on the substrate at an elevated temperature, forming an opening in the transparent region and penetrating through a portion of the electric circuit layer, forming a light emitting unit on the electric circuit layer in the first region, and forming an insulating layer on the substrate. At least a part of the insulating layer is formed in the opening.

A method for manufacturing an electronic device is disclosed. The electronic device has a first region and a transparent region. The method includes the steps of providing a substrate, forming an electric circuit layer on the substrate at an elevated temperature, forming an opening in the transparent region and penetrating through a portion of the electric circuit layer, forming a light emitting unit on the electric circuit layer in the first region, and forming an insulating layer on the substrate. At least a part of the insulating layer is formed in the opening.

A component carrier with an electrically insulating layer structure has opposed main surfaces, a through-hole, and an electrically conductive bridge structure connecting opposing sidewalls delimiting the through-hole. The sidewalls have a first tapering portion extending from a first main surface and a second tapering portion extending from a second main surface. A first demarcation surface faces the first main surface and a second demarcation surface faces the second main surface. A central bridge plane extends parallel to the first main surface and the second main surface and is at a vertical center between a lowermost point of the first demarcation surface and an uppermost point of the second demarcation surface. A first intersection point is between the central bridge plane and one of the sidewalls delimiting the through hole. A length of a shortest distance from the first intersection point to the first demarcation surface is at least 8 μm.

Examples described herein relate to a system that includes: a circuit board comprising a plurality of layers, first and second conductive connections, first and second trace portions, first, second, and third routings, and a via wherein: the first conductive connection is coupled to the first trace portion, the second conductive connection is coupled to the second trace portion, the first routing is formed in a first layer of the plurality of layers, the second routing is formed in a second layer of the plurality of layers, the third routing is formed in the first layer of the plurality of layers, a portion of the first routing overlaps with a portion of the second routing to provide a capacitive region, and the via conductively couples a portion of the second routing overlaps with a portion of the third routing.

Examples described herein relate to a system that includes: a circuit board comprising a plurality of layers, first and second conductive connections, first and second trace portions, first, second, and third routings, and a via wherein: the first conductive connection is coupled to the first trace portion, the second conductive connection is coupled to the second trace portion, the first routing is formed in a first layer of the plurality of layers, the second routing is formed in a second layer of the plurality of layers, the third routing is formed in the first layer of the plurality of layers, a portion of the first routing overlaps with a portion of the second routing to provide a capacitive region, and the via conductively couples a portion of the second routing overlaps with a portion of the third routing.

A circuit board with anti-corrosion properties, a method for manufacturing the circuit board, and an electronic device are provided. The circuit board includes a circuit substrate, a first protective layer, and a second protective layer. The circuit substrate includes a base layer and an outer wiring layer formed on the base layer. The circuit substrate further defines a via hole connected to the outer wiring layer. The first protective layer is formed on the outer wiring layer and an inner sidewall of the via hole, and is made of a white oil. The second protective layer is formed on the first protective layer.

The present invention discloses an ion beam lithography method based on an ion beam lithography system. The ion beam lithography system includes a roll-roll printer placed in a vacuum, and a medium-high-energy wide-range ion source, a medium-low-energy wide-range ion source and a low-energy ion source installed on the roll-roll printer. The ion beam lithography method includes: first coating a polyimide (PI) substrate with a dry film, etching the dry film according to a preset circuit pattern, then using the ion beam lithography system to deposit a wide-energy-range metal ion on the circuit pattern to form a film substrate, and finally stripping the dry film off the film substrate to obtain a printed circuit board (PCB).

Provided are: a structure with a conductive pattern that can be obtained in a simple manufacturing process and that exhibits favorable interlayer adhesion; and a method for manufacturing same. An embodiment of the present invention provides a structure with a conductive pattern, the structure comprising a base material, and a copper-containing conductive layer arranged on the surface of the base material, wherein when a principal surface of the conductive layer on the side facing the base material is a first principal surface, and a principal surface of the conductive layer on the opposite side from the first principal surface is a second principal surface, the conductive layer: has a porosity of 0.01 to 50 volume percent in a first principal surface-side region that extends from the first principal surface to a depth of 100 nm in the thickness direction of the conductive layer.