Patent classifications
H05K3/10
Systems and methods for hybrid glass and organic packaging for radio frequency electronics
An electronics package is disclosed. The electronics package includes a first radio frequency (RF) substrate layer, a second RF substrate layer, and a plurality of conductive layers disposed adjacent to at least one of the first RF substrate layer and the second RF substrate layer and including an inner conductive layer disposed between and adjacent to both the first RF substrate layer and the second RF substrate layer. The inner conductive layer bonds the first RF substrate layer to the second RF substrate layer. The electronics package also includes a plurality of conductive interconnects extending through the first RF substrate layer and the second RF substrate layer and electrically coupled between at least two of the plurality of conductive layers.
METHOD OF PRODUCING PRINTED CIRCUIT BOARDS AND PRINTED CIRCUIT BOARDS PRODUCED IN ACCORDANCE WITH THE METHOD
A method of producing a multilayer printed circuit board includes a metallic conductor structure including providing a base substrate including a film or plate and having first and second substrate sides, which base substrate at least partly consists of an electrically non-conductive organic polymer material and wherein the first substrate side is covered with a cover metal layer, partially removing the cover metal layer while subdividing the first substrate side into at least one first partial area, in which the first substrate side is free of the cover metal layer, and into at least one second partial area, in which the first substrate side is covered with the cover metal layer, and causing a plasma to act on the first substrate side with the aid of which plasma the polymer material is removed in the at least one first partial area while forming at least one trench.
METHODS AND SYSTEMS FOR FABRICATING 3D MULTIELECTRODE ARRAYS WITH 3D PRINTED ELECTRODES
Methods and systems for fabricating 3D electronic devices, such as multielectrode arrays, including metalized, 3D printed structures using integrated 3D printing and photolithography techniques are disclosed. As one embodiment, a multielectrode array comprises a flexible substrate, a plurality of photopatterned electrical traces spaced apart and insulated from one another on the substrate, and a plurality of 3D printed electrodes. Each 3D printed electrode comprises a photopolymer coated in metal and has a 3D structure that extends outward from the substrate, and each 3D printed electrode is electrically connected to a corresponding electrical trace of the plurality of photopatterned electrical traces.
METHODS AND SYSTEMS FOR FABRICATING 3D MULTIELECTRODE ARRAYS WITH 3D PRINTED ELECTRODES
Methods and systems for fabricating 3D electronic devices, such as multielectrode arrays, including metalized, 3D printed structures using integrated 3D printing and photolithography techniques are disclosed. As one embodiment, a multielectrode array comprises a flexible substrate, a plurality of photopatterned electrical traces spaced apart and insulated from one another on the substrate, and a plurality of 3D printed electrodes. Each 3D printed electrode comprises a photopolymer coated in metal and has a 3D structure that extends outward from the substrate, and each 3D printed electrode is electrically connected to a corresponding electrical trace of the plurality of photopatterned electrical traces.
CONFORMAL POWER DELIVERY STRUCTURES INCLUDING EMBEDDED PASSIVE DEVICES
A embedded passive structure, a microelectronic system, and an integrated circuit device assembly, and a method of forming the embedded passive structure. The embedded passive structure includes a base layer; a passive device attached to the base layer; a first power plane comprising metal and adjacent an upper surface of the base layer, the first power plane having a portion electrically coupled to a terminal of the passive device, wherein an upper surface of a combination of the first power plane and the passive device defines a recess; a second power plane comprising metal, the second power plane at least partially within the recess and having a lower surface that conforms with the upper surface of the combination; and a liner including a dielectric layer between the first power plane and the second power plane.
THIN FILM-BASED MICROFLUIDIC ELECTRONIC DEVICE, METHOD OF FORMING THEREOF, AND SKIN AND TISSUE ADHESIVE APPLICATIONS
There is provided a method of forming a thin film-based microfluidic electronic device. The method includes: providing a first elastomeric thin film layer on a substrate; depositing a first elastomer on the first elastomeric thin film by direct ink writing to form an elastomeric structure configured to define a microfluidic channel on the first elastomeric thin film layer; providing a second elastomeric thin film layer over the elastomeric structure to cover the microfluidic channel; providing a sacrificial layer on the second elastomeric thin film; depositing liquid metal into the microfluidic channel to form a conductor in the microfluidic channel; and electrically connecting the conductor to an electronic component. The thin film-based microfluidic electronic device is a tissue or skin adhesive sensor including a skin adhesive acoustic device.
MULTILAYER PRINTED CIRCUIT BOARD
Embodiments provide a multilayer printed circuit board intended to connect electronic components, the board comprising a stack of a plurality of conductive layers, the conductive layers comprising two surface layers and one or more internal layers, the board comprising one or more counterbored holes, each counterbored hole comprising a portion with metallization opening onto one of the two surface layers and a portion without metallization opening onto the other surface layer; the multilayer printed circuit board may advantageously comprise one or more metal pads, each metal pad being joined to one of the two surface layers so as to occult the portion without metallization of a corresponding counterbored hole.
MULTILAYER PRINTED CIRCUIT BOARD
Embodiments provide a multilayer printed circuit board intended to connect electronic components, the board comprising a stack of a plurality of conductive layers, the conductive layers comprising two surface layers and one or more internal layers, the board comprising one or more counterbored holes, each counterbored hole comprising a portion with metallization opening onto one of the two surface layers and a portion without metallization opening onto the other surface layer; the multilayer printed circuit board may advantageously comprise one or more metal pads, each metal pad being joined to one of the two surface layers so as to occult the portion without metallization of a corresponding counterbored hole.
Carrier board structure with an increased core-layer trace area and method for manufacturing same
Carrier board structure with an increased core-layer trace area and method for manufacturing the same are introduced. The carrier board structure comprises a core layer structure, a first circuit build-up structure, and a second circuit build-up structure. The core layer structure comprises a core layer, a signal transmission portion, and an embedded circuit layer, wherein the signal transmission portion and the embedded circuit layer are disposed inside the core layer and electrically connected. The first circuit build-up structure is disposed on the core layer on a same side as the embedded circuit layer and is electrically connected to the embedded circuit layer. The second circuit build-up structure is disposed on the core layer on a same side as the signal transmission portion, and is electrically connected to the first circuit build-up structure through the signal transmission portion and the embedded circuit layer.
Carrier board structure with an increased core-layer trace area and method for manufacturing same
Carrier board structure with an increased core-layer trace area and method for manufacturing the same are introduced. The carrier board structure comprises a core layer structure, a first circuit build-up structure, and a second circuit build-up structure. The core layer structure comprises a core layer, a signal transmission portion, and an embedded circuit layer, wherein the signal transmission portion and the embedded circuit layer are disposed inside the core layer and electrically connected. The first circuit build-up structure is disposed on the core layer on a same side as the embedded circuit layer and is electrically connected to the embedded circuit layer. The second circuit build-up structure is disposed on the core layer on a same side as the signal transmission portion, and is electrically connected to the first circuit build-up structure through the signal transmission portion and the embedded circuit layer.