Provided is a layout structure capable of reducing the parasitic capacitance between storage nodes of an SRAM cell using vertical nanowire (VNW) FETs. In the SRAM cell, a first storage node is connected to top electrodes of some transistors, and a second storage node is connected to bottom electrodes of other transistors. Accordingly, the first and second storage nodes have fewer regions adjacent to each other in a single layer.

Semiconductor structures are provided. A semiconductor structure includes a memory cell and a logic cell. The memory cell includes a latch circuit formed by two cross-coupled inverters, and a pass-gate transistor coupling an output of the latch circuit to a bit line. A first source/drain region of the pass-gate transistor is electrically connected to the bit line through a first contact over the first source/drain region and a first via over the first contact. A second source/drain region of a transistor of the logic cell is electrically connected to a local interconnect line through a second contact over the second source/drain region and a second via over the second contact. Height of the second via is greater than height of the first via. The local interconnect line and the bit line are formed in the same metal layer. The bit line is thicker than the local interconnect line.

A method of designing a circuit is provided. The method includes: providing a circuit; selecting a first NMOS fin field-effect transistor (FinFET) in the circuit; and replacing the first NMOS FinFET having a first fin number with a second NMOS FinFET having a second fin number and a third NMOS FinFET having a third fin number, wherein the sum of the second fin number and the third fin number is equal to the first fin number.

A memory device including: active regions; gate electrodes which are substantially aligned relative to four corresponding track lines such that the memory device has a width of four contacted poly pitch (4 CPP) and are electrically coupled to the active regions; contact-to-transistor-component structures (MD structures) which are electrically coupled to the active regions, and are interspersed among corresponding ones of the gate electrodes; via-to-gate/MD (VGD) structures which are electrically coupled to the gate electrodes and the MD structures; conductive segments which are in a first layer of metallization (M_1st layer), and are electrically coupled to the VGD structures; buried contact-to-transistor-component structures (BVD structures) which are electrically coupled to the active regions; and buried conductive segments which are in a first buried layer of metallization (BM_1st layer), and are electrically coupled to the BVD structures, and correspondingly provide a first reference voltage or a second reference voltage.

A memory device includes a conductive segment, first and second rows of memory cells. The conductive segment receives a first reference voltage signal. The first row of memory cells is coupled to a first word line. The second row of memory cells is coupled to a second word line. The first row of memory cells includes first and second memory cells. The first memory cell is coupled to the conductive segment to receive the first reference voltage signal. The second row of memory cells includes third and fourth memory cells. The third memory cell is coupled to the conductive segment to receive the first reference voltage signal. The first and third memory cells share the conductive segment, and the third memory cell is arranged between the first and second memory cells. The second memory cell is arranged between the third and fourth memory cells.

SRAM arrays are provided. A SRAM array includes a plurality of SRAM cells and a plurality of well strap cells. Each of the SRAM cells arranged in the same column of the cell array includes a first transistor formed in a first P-type well region of a substrate, a second transistor formed in an N-type well region of the substrate, and a third transistor formed in a second P-type well region of the substrate. Each well strap cell is arranged on one of the columns in the cell array and includes a first P-well strap structure formed on the first P-type well region, a second P-well strap structure formed on the second P-type well region, and an N-well strap structure formed on the N-type well region. The first and second P-well strap structures and the N-well strap structure are separated from the SRAM cells by a dummy area.

A memory device includes a first field effect transistor (FET) stack on a first bottom source/drain region, which includes a first vertical transport field effect transistor (VTFET) device between a second VTFET device and the first source/drain region, and a second FET stack on a second bottom source/drain region, which includes a third VTFET device between a fourth VTFET device and the bottom source/drain region. The memory device includes a third FET stack on a third bottom source/drain region, which includes a fifth VTFET between a sixth VTFET and the third source/drain region, which is laterally adjacent to the first and second source/drain regions. The memory device includes a first electrical connection interconnecting a gate structure of the third VTFET with a gate structure of the fifth VTFET, and a second electrical connection interconnecting a gate structure of the second VTFET with a gate structure of the sixth VTFET.

First and second sensing circuits are coupled to first and second data lines, respectively, and sense levels of current leakage or a memory cell state on the first and second data lines. First and second keeper circuits are coupled to the first and second data lines, respectively, and drive the first and second data lines by a voltage supply through biased transistors. First and second leakage latches are coupled to receive and latch state of signals output from the first and second sensing circuits, respectively. A control circuit is coupled to the first leakage latch, second leakage latch, and outputs of the first and second sensing circuits. The control circuit is configured to select either the signal output from the first sensing circuit or the signal output from the second sensing circuit in response to states of the first and second leakage latches.

The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a first fin structure disposed over an n-type FinFET (NFET) region of a substrate. The first fin structure includes a silicon (Si) layer, a silicon germanium oxide (SiGeO) layer disposed over the silicon layer and a germanium (Ge) feature disposed over the SiGeO layer. The device also includes a second fin structure over the substrate in a p-type FinFET (PFET) region. The second fin structure includes the silicon (Si) layer, a recessed silicon germanium oxide (SiGeO) layer disposed over the silicon layer, an epitaxial silicon germanium (SiGe) layer disposed over the recessed SiGeO layer and the germanium (Ge) feature disposed over the epitaxial SiGe layer.

Fin-based well straps are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a FinFET disposed over a doped region of a first type dopant. The FinFET includes a first fin structure doped with a first dopant concentration of the first type dopant and first source/drain features of a second type dopant. The IC device further includes a fin-based well strap disposed over the doped region of the first type dopant. The fin-based well strap connects the doped region to a voltage. The fin-based well strap includes a second fin structure doped with a second dopant concentration of the first type dopant and second source/drain features of the first type dopant. The second dopant concentration is greater than (for example, at least three times greater than) the first dopant concentration.