A device includes a first transistor including a first drain/source terminal and a second transistor including a first gate terminal. A first conductive path is electrically connected between the first drain/source terminal and the first gate terminal. The first conductive path includes a first conductive via electrically connected between the first drain/source terminal and a first track of a first conductive layer, and a second conductive via electrically connected between the first track of the first conductive layer and a first track of a second conductive layer.

A wafer having a semiconductor substrate including a peripheral region and a central region, an insulating layer and a semiconductor layer is prepared first. Next, a plurality of trenches penetrating through the semiconductor layer and the insulating layer and reaching an inside of the semiconductor substrate are formed. Next, an inside of each of the plurality of trenches is filled with an insulating film, so that a plurality of element isolating portions is formed. Next, in the central region, the semiconductor layer exposed from a resist pattern is removed. The end portion closest to the outer edge of the semiconductor substrate among ends of the resist pattern used for removing the semiconductor layer in the central region is formed so as to be positioned closer to the outer edge of the semiconductor substrate than a position of the end portion closest to the outer edge of the semiconductor substrate among ends of the resist pattern used for forming the trenches.

A semiconductor device includes a first active fin having first fin-type patterns and a first separation region therebetween; a second active fin having second fin-type patterns and a second separation region therebetween, where a first trench region between the first and second active fins has a first depth, and the first and second fin-type patterns are merged by the first trench region; a third active fin adjacent to the first active fin, where a second trench region between the first and third active fins has a second depth that is greater than the first depth; and at least one first gate line intersecting the first and second active fins and the third active fins.

A memory device includes a first field effect transistor (FET) stack on a first bottom source/drain region, which includes a first vertical transport field effect transistor (VTFET) device between a second VTFET device and the first source/drain region, and a second FET stack on a second bottom source/drain region, which includes a third VTFET device between a fourth VTFET device and the bottom source/drain region. The memory device includes a third FET stack on a third bottom source/drain region, which includes a fifth VTFET between a sixth VTFET and the third source/drain region, which is laterally adjacent to the first and second source/drain regions. The memory device includes a first electrical connection interconnecting a gate structure of the third VTFET with a gate structure of the fifth VTFET, and a second electrical connection interconnecting a gate structure of the second VTFET with a gate structure of the sixth VTFET.

Examples of an integrated circuit with a contacting gate structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a memory cell that includes a plurality of fins and a gate extending over a first fin of the plurality of fins and a second fin of the plurality of fins. The gate includes a gate electrode that physically contacts the first fin and a gate dielectric disposed between the gate electrode and the second fin. In some such examples, the first fin includes a source/drain region and a doped region that physically contacts the gate electrode.

Integrated circuit devices and methods of forming the same are provided. The methods may include forming a dummy channel region and an active region of a substrate, forming a bottom source/drain region on the active region, forming a gate electrode on one of opposing side surfaces of the dummy channel region, and forming first and second spacers on the opposing side surfaces of the dummy channel region, respectively. The gate electrode may include a first portion on the one of the opposing side surfaces of the dummy channel region and a second portion between the bottom source/drain region and the first spacer. The methods may also include forming a bottom source/drain contact by replacing the first portion of the gate electrode with a conductive material. The bottom source/drain contact may electrically connect the second portion of the gate electrode to the bottom source/drain region.

A semiconductor device includes a first metal-oxide semiconductor (MOS) transistor on a first substrate, a first interlayer dielectric (ILD) layer on the first MOS transistor, a second substrate on the first ILD layer, and a second MOS transistor on a second substrate. Preferably, the semiconductor device includes a static random access memory (SRAM) and the SRAM includes a first pull-up device, a second pull-up device, a first pull-down device, a second pull-down device, a first pass-gate device, a second pass-gate device, a read port pull-down device, and a read port pass-gate device, in which the read port pull-down device includes the first MOS transistor and the read port pass-gate device includes the second MOS transistor.

To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at most 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other.

An integrated circuit structure includes a Static Random Access Memory (SRAM) cell, which includes a read port and a write port. The write port includes a first pull-up Metal-Oxide Semiconductor (MOS) device and a second pull-up MOS device, and a first pull-down MOS device and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device. The integrated circuit structure further includes a first metal layer, with a bit-line, a CVdd line, and a first CVss line in the first metal layer, a second metal layer over the first metal layer, and a third metal layer over the second metal layer. A write word-line is in the second metal layer. A read word-line is in the third metal layer.

An integrated circuit includes: a dual port Static Random Access Memory (SRAM) cell including a plurality of transistors; a bit line pair connected to the dual port SRAM cell, the bit line pair including a first bit line and a second bit line spaced apart from each other in a first direction and extending in a second direction perpendicular to the first direction; a power line group including a plurality of power lines spaced apart from each other in the first direction, spaced apart from the bit line pair placed in the first direction, and extending in the second direction, the power line group being configured to apply a voltage to the dual-port SRAM cell; and a first word line provided between the first bit line and the second bit line and connected to the dual port SRAM cell.