Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a processor, an array of static random-access memory (SRAM) cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

A memory device includes a first isolation cell, a first memory array of a first memory segment, a second memory array of a second memory segment, a first decoder cell of the first memory segment and a second decoder cell of the second memory segment. The first isolation cell extends in a first direction. The first memory array of the first memory segment abuts a first boundary of the first isolation cell in a second direction different from the first direction. The second memory array of the second memory segment abuts a second boundary, opposite to the first boundary, of the first isolation cell in the second direction. The first decoder cell of the first memory segment and the second decoder cell of the second memory segment are arranged on opposite sides of the first isolation cell.

A semiconductor device includes a substrate having a first memory cell and a second memory cell, the first and second memory cells being adjacent to each other in a first direction, first to fourth memory fins adjacent to each other in the first direction in the first memory cell, the first to fourth memory fins protruding from the substrate, fifth to eighth memory fins adjacent to each other in the first direction in the second memory cell, the fifth to eighth memory fins protruding from the substrate, and a first shallow device isolation layer between the fourth memory fin and the fifth memory fin, a sidewall of the first shallow device isolation layer having an inflection point.

A semiconductor device structure is provided. The semiconductor device structure includes a first device formed over a substrate, and the first device includes a first fin structure. The semiconductor device structure also includes a second device formed over or below the first device, and the second device includes a plurality of second nanostructures stacked in a vertical direction.

The present disclosure provides a semiconductor structure, including: a first layer including a logic device; and a second layer over the first layer, including a first type memory device, a though silicon via (TSV) electrically connecting the logic device and the first type memory device. A method of forming semiconductor structure is also disclosed.

A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region.

Techniques herein include methods of forming higher density circuits by combining multiple substrates via stacking and bonding of individual substrates. High voltage and low voltage devices along with 3D NAND devises are fabricated on a first wafer, and high voltage and low voltage devices and/or memory are then fabricated on a second wafer and/or third wafer.

A semiconductor device includes a first device plane over a substrate. The first device plane includes a first transistor device having a first source/drain (S/D) region formed in an S/D channel. A second device plane is formed over the first device plane. The second device plane includes a second transistor device having a second gate formed in a gate channel which is adjacent to the S/D channel. A first inter-level connection is formed from the first S/D region of the first transistor device to the second gate of the second transistor device. The first inter-level connection includes a lateral offset from the S/D channel to the gate channel.

A semiconductor integrated circuit device using nanowire FETs has a circuit block in which a plurality of cell rows each including a plurality of standard cells lined up in the X direction are placed side by side in the Y direction. The plurality of standard cells each include a plurality of nanowires that extend in the X direction and are placed at a predetermined pitch in the Y direction. The plurality of standard cells have a cell height, that is a size in the Y direction, M times (M is an odd number) as large as half the pitch of the nanowires.

A semiconductor device includes a substrate including a first region and a second region, memory transistors on the first region, a first interconnection layer on the memory transistors and including first interconnection lines, and a second interconnection layer on the first interconnection layer and including second interconnection lines. The second interconnection lines on the first region include a first line extending along a first direction and spaced from the second region by a first distance along the first direction, and a second line extending along the first direction, spaced from the first line along a second direction intersecting the first direction, and having a width smaller than that of the first line. The first line includes a protrusion extending along a third direction toward the substrate. The protrusion is spaced from the second region by a second distance along the first direction greater than the first distance.