Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.

A 3D semiconductor device including: a first single crystal layer with first transistors; overlaid by a first metal layer; a second metal layer overlaying the first metal layer and being overlaid by a third metal layer; a logic gates including at least the first metal layer interconnecting the first transistors; second transistors disposed atop the third metal layer; third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, and at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or third transistors, sense amplifier circuit(s) for each of the memory mini arrays, the second metal layer provides a greater current carrying capacity than the third metal layer.

A semiconductor device that is suitable for high integration is provided. A first layer provided with a first transistor including an oxide semiconductor, over a substrate; a second layer over the first layer; a third layer provided with a second transistor including an oxide semiconductor, over the second layer; a fourth layer between the first layer and the second layer; and a fifth layer between the second layer and the third layer are included. The total internal stress of the first layer and the total internal stress of the third layer act in a first direction, the total internal stress of the second layer acts in the direction opposite to the first direction, and the fourth layer and the fifth layer each include a film having a barrier property.

A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.

Described herein are integrated circuit (IC) devices that include devices that include fin-based field-effect transistors (FinFETs) integrated over gate-all-around (GAA) transistors. The GAA transistors may serve to provide high-performance compute logic, and may be relatively low-voltage transistors, while FinFETs may be more suitable than GAA transistors for providing high-voltage transistors, and, therefore, may serve to provide peripheral logic for backend memory arrays implemented over the same support structure over which the GAA transistors and the FinFETs are provided. Such an arrangement may address the fundamental voltage incompatibility by integrating a mix of FinFETs and GAA transistors in stacked complimentary FET (CFET) architecture to enable embedded 1T-1X based memories.

A semiconductor device includes a first conductive layer extending along a first direction, a semiconductor layer extending along a second direction crossing the first direction, penetrating the first conductive layer, and including an oxide semiconductor, a first insulating layer between the first conductive layer and the semiconductor layer, a second conductive layer provided on one side of the semiconductor layer in the second direction and electrically connected thereto, a third conductive layer provided on the other side of the semiconductor layer in the second direction and electrically connected thereto, an electric conductor extending from the third conductive layer toward the second conductive layer along the semiconductor layer, and a charge storage film between the semiconductor layer and the electric conductor.

A semiconductor structure includes: a substrate; a gate structure on the substrate; and an interconnect structure including a first interconnect sub-structure and a second interconnect sub-structure, where the second interconnect sub-structure protrudes from the first interconnect sub-structure. The first interconnect sub-structure is connected with the substrate, and the second interconnect sub-structure is connected with a top of the gate structure.

A semiconductor device includes bit lines extending in a first direction on a substrate, a lower contact connected to the substrate between two adjacent ones of the bit lines, a landing pad on the lower contact, and an insulating structure surrounding a sidewall of the landing pad, the insulating structure including a first insulating pattern having a top surface at a lower level than a top surface of the landing pad, and a second insulating pattern on the top surface of the first insulating pattern.

An N.sup.+ layer 11a and N.sup.+ layers 13a to 13d that are disposed on both ends of Si pillars 12a to 12d standing on a substrate 10 in a vertical direction, a TiN layer 18a that surrounds a gate HfO.sub.2 layer 17a surrounding the Si pillars 12a to 12d and that extends between the Si pillars 12a and 12b, a TiN layer 18b that surrounds the gate HfO.sub.2 layer 17a and that extends between the Si pillars 12c and 12d, a TiN layer 26a that surrounds a gate HfO.sub.2 layer 17b surrounding the Si pillars 12a to 12d and that extends between the Si pillars 12a and 12b, and a TiN layer 26b that surrounds the gate HfO.sub.2 layer 17b and that extends between the Si pillars 12c and 12d are formed. Voltages applied to the N.sup.+ layers 11a and 13a to 13d and the TiN layers 18a, 18b, 26a, and 26b are controlled to perform a data write operation of retaining, inside the Si pillars 12a to 12d, a group of positive holes generated by an impact ionization phenomenon and a data erase operation of discharging the group of positive holes from the inside of the Si pillars 12a to 12d.

Present invention relates to a semiconductor memory device. A semiconductor memory device according to the present invention may comprise: a memory cell array including a plurality of memory cells over a substrate, the plurality of memory cells repeatedly arranged in horizontal direction and a vertical direction, the horizontal direction parallel to a surface of the substrate, the vertical direction perpendicular to the surface of the substrate, a bit line coupled to the memory cells arranged in the vertical direction, and a word line coupled to the memory cells arranged in the horizontal direction, wherein each of the memory cells comprises a capacitor comprising a storage node and a plate node, and the plate nodes of the capacitors are coupled to each other in the vertical direction and are spaced apart from each other in the horizontal direction.