A 3D semiconductor device, the device including: a first level including a plurality of first metal layers; a second level, where the second level overlays the first level, where the second level includes at least one single crystal silicon layer, where the second level includes a plurality of transistors, where each transistor of the plurality of transistors includes a single crystal channel, where the second level includes a plurality of second metal layers, where the plurality of second metal layers include interconnections between the transistors of the plurality of transistors, where the second level is overlaid by a first isolation layer; and a connective path between the plurality of transistors and the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, and where at least one of the plurality of transistors includes a gate all around structure.

A semiconductor device includes a substrate including a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region, cell active patterns on the cell region of the substrate, peripheral active patterns on the peripheral region of the substrate, a boundary insulating pattern disposed on the boundary region of the substrate and disposed between the cell active patterns and the peripheral active patterns, and a bumper pattern disposed on the cell region of the substrate and disposed between the boundary insulating pattern and the cell active patterns. A width of the bumper pattern in a first direction parallel to a top surface of the substrate is greater than a width of each of the cell active patterns in the first direction.

Provided is a landing pad structure including a substrate, a plurality of landing pads, a guard ring, and an edge pattern. The substrate includes a cell region, a periphery region, and a guard ring region located between the cell region and the periphery region. The landing pads are arranged on the substrate in the cell region in a hexagonal close packing (HCP) configuration. The guard ring is disposed on the substrate in the guard ring region in a strip form. The edge pattern is disposed on the substrate in the cell region and close to the guard ring region. A method of manufacturing the landing pad structure is also provided.

A semiconductor device includes a substrate including a cell array region and a peripheral circuit region, capacitors on the cell array region of the substrate, peripheral transistors on the peripheral circuit region of the substrate, a first upper interlayer insulating layer on the capacitors and the peripheral transistors, a first upper contact electrically connected to at least one of the peripheral transistors, the first upper contact penetrating the first upper interlayer insulating layer, a first upper interconnection line provided on the first upper interlayer insulating layer and electrically connected to the first upper contact, a second upper interlayer insulating layer covering the first upper interconnection line, and a first blocking layer between the first upper interlayer insulating layer and the second upper interlayer insulating layer. The first blocking layer is absent between the first upper interconnection line and the first upper interlayer insulating layer.

Semiconductor devices including vertically-stacked combination memory devices and associated systems and methods are disclosed herein. The vertically-stacked combination memory devices include at least one volatile memory die and at least one non-volatile memory die stacked on top of each other. The corresponding stack may be attached to a controller die that is configured to provide interface for the attached volatile and non-volatile memory dies.

Disclosed are semiconductor devices and their fabrication methods. The method includes forming an etching target on a substrate including cell and key regions, forming lower and upper mask layers on the etching target, performing photolithography to form an upper mask pattern including a hole on the cell region, a preliminary key pattern on the key region, a bar pattern on the key region, and a trench between the preliminary key pattern and the bar pattern, forming pillar and dam patterns filling the hole and the trench, performing photolithography to remove the upper mask pattern except for the bar pattern, using the pillar pattern, the dam pattern, and the bar pattern as an etching mask to form a lower mask pattern, and using the lower mask pattern as an etching mask to form an etching target pattern on the cell region and a key pattern on the key region.

A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming peripheral circuitry in and/or on the first level, and includes first single crystal transistors; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming second level disposed on top of the second metal layer; performing a first lithography step; forming a third level on top of the second level; performing a second lithography step; processing steps to form first memory cells within the second level and second memory cells within the third level, where the plurality of first memory cells include at least one second transistor, and the plurality of second memory cells include at least one third transistor; and deposit a gate electrode for second and third transistors simultaneously.

The invention provides a semiconductor storage device including a substrate, a plurality of active areas which are arranged along an oblique direction, a dummy active area pattern, and the dummy active area pattern comprises a first edge principal axis pattern and a plurality of first long branches and a plurality of short branches connecting edge principal axis patterns, and a plurality of storage nodes are in contact with each other. According to the invention, a part of the storage node contacts are arranged on the dummy active area pattern, so that the difficulty of the manufacturing process can be reduced, and the surrounding storage node contacts can serve as protection structures to protect components and prevent the components from being physically or electrically affected.

The present application provides a memory cell, a memory array and a method for preparing the memory cell. The memory cell includes an active area, an isolation structure and a contact enhancement layer. The active area is a surface portion of a semiconductor substrate. A top surface of the active area has a slop part descending toward an edge of the active area within a peripheral region of the active area. The isolation structure is formed in a trench of the semiconductor substrate laterally surrounding the active area. The contact enhancement layer covers the edge of the active area and in lateral contact with the isolation structure. The slope part of the top surface of the active area is covered by the contact enhancement layer, and the contact enhancement layer is formed of a semiconductor material.

A memory device includes a substrate including first and second regions, the first region having first wordlines and first bitlines, and the second region having second wordlines and second bitlines, a first memory cell array including first memory cells in the first region, the first memory cell array having volatility, and each of the first memory cells including a cell switch having a first channel region adjacent to a corresponding first wordline of the first wordlines, and a capacitor connected to the cell switch, and a second memory cell array including second memory cells in the second region, the second memory cell array having non-volatility, and each of the second memory cells including a second channel region adjacent to a corresponding second wordline of the second wordlines, and a ferroelectric layer between the corresponding second wordline of the second wordlines and the second channel region.