A semiconductor device includes a substrate including cell and peripheral regions. Landing pads and contact plugs are on the cell and peripheral regions, respectively. A first filler pattern fills regions between the landing pads and between the contact plugs. Outer voids are in the first filler pattern and include first and second outer voids on the cell and peripheral regions, respectively. A second filler pattern covers the first filler pattern and the contact plugs and fills at least a portion of the second outer void. An inner void is in the second outer void and enclosed by the second filler pattern. The first and second filler patterns include the same material. On the cell region, at least a portion of the second filler pattern is located below top surfaces of the landing pads, and a bottom surface of the second filler pattern is partially exposed by the first outer void.

A semiconductor device is provided. The semiconductor device includes a substrate, device isolation films defining an active region in the substrate, the active region defined in the substrate by the device isolation films, a gate pattern formed in the active region, and source/drain regions on both sides of the gate pattern, in the active region, the source/drain regions include first parts, which are doped with carbon monoxide (CO) ions and are recrystallized.

A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer and control circuits; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where each of the first memory cells include one first transistor, where each of the second memory cells include one second transistor, where at least one of the first or second transistors has a channel, a source, and a drain having a same doping type.

A method of manufacturing a semiconductor device includes preparing a substrate including cell regions and a scribe lane region, forming circuit blocks in the cell regions of the substrate, the substrate including a first surface and a second surface, forming a bias pad on the first surface of the substrate, such that the bias pad is in the scribe lane region of the substrate, bonding a deuterium exchange structure to the second surface of the substrate, implanting deuterium into the deuterium exchange structure using plasma processing, and applying a first voltage to the bias pad, such that the deuterium is diffused from the deuterium exchange structure into the substrate through the second surface of the substrate.

A method for producing a 3D memory device including: providing a first level including a single crystal layer and control circuits, where the control circuits include a plurality of first transistors; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; performing processing steps to form a plurality of first memory cells within the second level, where each of the first memory cells include one of a plurality of second transistors, where the control circuits include memory peripheral circuits, where at least one first memory cell is at least partially atop a portion of the memory peripheral circuits, and where fabrication processing of the first transistors accounts for a temperature and time associated with processing the second level and the plurality of second transistors by adjusting a process thermal budget of the first level accordingly.

A semiconductor device includes an active region, and an edge seal formed on at least a portion of an outer edge of the active region. The edge seal includes a first stacked body having a first conductive layer, and a second stacked body having a second conductive layer. The first conductive layer is coupled to a first voltage, the second conductive layer is coupled to a second voltage different from the first voltage, and the first conductive layer faces the second conductive layer.

The present application provides a manufacturing method of a memory. The manufacturing method includes: providing a substrate, where the substrate includes a core region and a peripheral region, and a first barrier layer is provided in the core region; laminating and forming a first conductive layer and a first mask layer on the substrate in sequence; etching the first mask layer, the first conductive layer, and the first barrier layer in the core region, to form a first etched hole; etching the substrate along the first etched hole, to form a bit line contact hole; removing the first mask layer and the first conductive layer in the core region and located around the bit line contact hole; and forming a bit line contact in the bit line contact hole.

A method includes forming a stack of material layers to cover an array region and a periphery region of a substrate. A first patterned mask layer is formed, and the pattern of the first patterned mask layer is transferred to the stack of material layers, thereby forming a first array pattern and a first periphery pattern respectively in the array and periphery regions. A second patterned mask layer is provided above the first array and periphery patterns. The pattern of the second patterned mask is not aligned with the pattern of the first patterned mask. The pattern of the second patterned mask layer is transferred to form the first and second sacrificial patterns respectively in the array and periphery regions. The first array pattern, the first and second sacrificial patterns, and the first periphery pattern are simultaneously transferred to form a second array pattern and a second periphery pattern.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second transistors each include at least two side-gates, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.

A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming peripheral circuitry in and/or on the first level, and includes first single crystal transistors; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming second level disposed on top of the second metal layer; performing a first lithography step; forming a third level on top of the second level; performing a second lithography step; processing steps to form first memory cells within the second level and second memory cells within the third level, where the plurality of first memory cells include at least one second transistor, and the plurality of second memory cells include at least one third transistor; and deposit a gate electrode for second and third transistors simultaneously.