A one time programmable memory device includes a field effect transistor and an antifuse structure. A first node of the antifuse structure includes, or is electrically connected to, the drain region of the field effect transistor. The antifuse structure includes an antifuse dielectric layer and a second node on, or over, the antifuse dielectric layer. One of the first node and the second node includes the drain region or a metal via structure formed within a via cavity extending through an interlayer dielectric material layer that overlies the field effect transistor.

A programmable cell includes a semiconductor-on-insulator substrate, a program gate, and a word line gate. The semiconductor-on-insulator substrate includes a semiconductor layer. The semiconductor layer includes a first doped source/drain region, a second doped source/drain region and a region comprising germanium. The program gate is disposed above the region comprising germanium and includes a first gate dielectric layer disposed below a gate conductor. The word line gate is disposed between the first doped source/drain region and the second doped source/drain region.

An anti-fuse device includes a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and a salicide layer formed on a first portion of the gate electrode such that a second portion of the gate electrode omits the salicide layer, wherein a hard breakdown of at least a portion of the gate insulating film at a time of programming the anti-fuse device.

Embodiments provide an anti-fuse storage layout and a circuit thereof, and an anti-fuse memory and a design method thereof. The anti-fuse storage layout includes: active regions extending along a first direction and being discretely arranged along a second direction, each of the active regions including at least two memory cell regions arranged along the first direction, each of the at least two memory cell regions including an anti-fuse region and a control region arranged along the first direction, and the control regions of the adjacent memory cell regions being adjacent to each other along the first direction; a word line region extending along the second direction and intersecting with the control region; an electrical connection region extending along the second direction and intersecting with the anti-fuse region; and a programming control region extending along a third direction and being positioned at one side of the corresponding active region.

Embodiments provide an anti-fuse storage layout and a circuit thereof, and an anti-fuse memory and a design method thereof. The anti-fuse storage layout includes: active regions extending along a first direction and being discretely arranged along a second direction, each of the active regions including at least two memory cell regions arranged along the first direction, each of the at least two memory cell regions including an anti-fuse region and a control region arranged along the first direction, and the control regions of the adjacent memory cell regions being adjacent to each other along the first direction; a word line region extending along the second direction and intersecting with the control region; an electrical connection region extending along the second direction and intersecting with the anti-fuse region; and a programming control region extending along a third direction and being positioned at one side of the corresponding active region.

Embodiments of the present disclosure relate to the field of semiconductor technology, and provide an anti-fuse memory and a control method thereof. The anti-fuse memory is configured to generate a programming pulse signal based on a row strobe signal, a word line of the anti-fuse memory array is configured to receive the row strobe signal, and the anti-fuse memory array is programmed in response to the programming pulse signal. The embodiments of the present disclosure are at least advantageous to improving accuracy of reading data from the anti-fuse memory array and improving yield of the anti-fuse memory.

Embodiments of the present disclosure relate to the field of semiconductor technology, and provide an anti-fuse memory and a control method thereof. The anti-fuse memory is configured to generate a programming pulse signal based on a row strobe signal, a word line of the anti-fuse memory array is configured to receive the row strobe signal, and the anti-fuse memory array is programmed in response to the programming pulse signal. The embodiments of the present disclosure are at least advantageous to improving accuracy of reading data from the anti-fuse memory array and improving yield of the anti-fuse memory.

An anti-fuse readout circuit, an anti-fuse memory, and a testing method are provided. The anti-fuse readout circuit includes: a latch circuit configured to latch data read out from an anti-fuse storage array; and a transmission circuit connected to an output terminal of the latch circuit, the transmission circuit being configured to transmit data latched in the latch circuit to a data port in response to a read test command.

An anti-fuse readout circuit, an anti-fuse memory, and a testing method are provided. The anti-fuse readout circuit includes: a latch circuit configured to latch data read out from an anti-fuse storage array; and a transmission circuit connected to an output terminal of the latch circuit, the transmission circuit being configured to transmit data latched in the latch circuit to a data port in response to a read test command.

Device structures for an anti-fuse and methods for manufacturing device structures for an anti-fuse. The anti-fuse includes a first terminal comprised of a fin. The fin includes a section with an edge and inclined surfaces that intersect at the edge. The anti-fuse further includes a second terminal covering the edge and the inclined surfaces of the fin, and an isolation dielectric layer on the inclined surfaces and the edge of the fin. The second terminal is separated from the edge and inclined surfaces of the fin by the isolation dielectric layer. The edge and inclined surfaces on the firm may be formed by oxidizing an upper section of the fin in a trench to form an oxide layer, and then removing the oxide layer to expose the edge and inclined surfaces.