An integrated circuit includes a TSV extending from a first surface of a semiconductor substrate to a second surface of the semiconductor substrate and having a first end and a second end, and a non-volatile repair circuit. The non-volatile repair circuit includes a one-time programmable (OTP) element having a programming terminal, wherein in response to an application of a fuse voltage to the programming terminal, the OTP element electrically couples the first end of the TSV to the second end of the TSV.

A memory cell includes a semiconductor substrate, a transistor, and a first anti-fuse structure. The transistor is above the semiconductor substrate. The first anti-fuse structure is above the semiconductor substrate and adjacent the transistor, and includes a first terminal and a second terminal. The first terminal of the first anti-fuse structure is in the semiconductor substrate and laterally surrounds the transistor. The second terminal of the first anti-fuse structure is above and spaced apart from the first terminal of the first anti-fuse structure.

The present application discloses a semiconductor device with a P-N junction isolation structure and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first well layer positioned in the substrate and having a first electrical type, a bottom conductive layer positioned in the first well layer and having a second electrical type opposite to the first electrical type, a first insulating layer positioned on the bottom conductive layer, an isolation-mask layer positioned on the substrate and enclosing the first insulating layer, a first conductive line positioned on the first insulating layer, and a bias layer positioned in the first well layer and spaced apart from the bottom conductive layer. The bottom conductive layer, the first insulating layer, and the first conductive line together configure a programmable unit.

A semiconductor device includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.

A semiconductor device includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.

An insulating film, which is sandwiched between a gate electrode formed on an SOI layer constituting an SOI substrate and an epitaxial layer formed on the SOI layer and including a high-concentration diffusion region and is formed in contact with a side wall of the gate electrode, is set as a target of dielectric breakdown in a write operation in an anti-fuse element.

A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming a first metal layer on top of first level; forming a second metal layer on top of the first metal layer; forming at least one second level above the second metal layer; performing a first lithography step on the second level; forming a third level on top of the second level; performing a second lithography step on the third level; perform processing steps to form first memory cells within the second level and second memory cells within the third level, where first memory cells include at least one second transistor, and the second memory cells include at least one third transistor; and deposit a gate electrode for the second and the third transistors simultaneously.

A charge pump circuit includes a first charge pump unit and a second charge pump unit. The first charge pump unit pumps an input voltage to output a first pumped voltage according to a first clock signal, a second clock signal and a third clock signal. The second charge pump unit pumps the first pumped voltage to output a second pumped voltage according to the first clock signal, a fourth clock signal and the third clock signal. The first clock signal and the third clock signal are non-overlapping clock signals. A falling edge of the second clock signal leads a rising edge of the first clock signal. A falling edge of the fourth clock signal leads a rising edge of the third clock signal.

A non-volatile memory having a double metal layout is provided that includes a first fuse fabricated on a first conductive layer of the integrated circuit, a second fuse fabricated on a second conductive layer of the integrated circuit, and a transistor fabricated on front-end-of-the-line (FEOL) structure of the integrated circuit. A first memory cell of the non-volatile memory is provided by a first memory circuit comprising the first fuse and the transistor, and a second memory cell of the non-volatile memory is provided by a second memory circuit comprising the second fuse and the transistor.

The present disclosure provides a method for fabricating a semiconductor device. The method includes providing a substrate, forming a first well layer in the substrate and having a first electrical type, forming an isolation-mask layer on the first well layer, forming mask openings along the isolation-mask layer to expose portions of the first well layer, forming bottom conductive layers in the portions of the first well layer, forming a bias layer in the first well layer and spaced apart from the bottom conductive layers, forming first insulating layers on the bottom conductive layers, forming first conductive lines on the first insulating layers and parallel to each other. The bottom conductive layers have a second electrical type opposite to the first electrical type. The bottom conductive layers, the first insulating layers, the first conductive lines together configure programmable units.