A device includes a programmable ROM circuit, an address circuit, and a processor. The programmable ROM circuit includes multiple physically contiguous pairs of bit-cells, each pair of bit-cells includes an active layer trace extending continuously across both of the bit-cells, each pair of bit-cells comprises a shared contact layer point when the pair of bit-cells is programmed to a value of one and no shared contact layer point when the pair of bit-cells is programmed to a value of zero. The address circuit is coupled to the programmable ROM circuit and configured to address only a first bit-cell of each pair of bit-cells. The processor is coupled to the address circuit and the programmable ROM circuit and configured to use the address circuit to read data from one or more pairs of bit-cells of the programmable ROM circuit.

A 3D semiconductor device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where a second metal layer is disposed atop the first metal layer; a plurality of logic gates including the first metal layer and first transistors; a plurality of second transistors disposed atop the second metal layer; a plurality of third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, where the memory array includes at least four memory mini arrays, where each of the mini arrays includes at least two rows by two columns of memory cells, where each memory cell includes one of the second transistors or one of the third transistors, and where one of the second transistors is self-aligned to one of the third transistors, being processed following a same lithography step.

An anti-fuse structure is provided that contains multiple breakdown points which result in low resistance after the anti-fuse structure is blown. The anti-fuse structure is provided using a method that is compatible with existing FinFET device processing flows without requiring any additional processing steps.

The present invention provides a non-overlapped-extension-implantation (NOI) nonvolatile memory device capable of being treated with anti-fuse operation. Differing from conventional anti-fuse memory devices, the structure and fabrication of this NOI nonvolatile memory device are complied with currently-used standard COMS processes; that is, the NOI nonvolatile memory device provided by the present invention can be manufactured through the standard COMS processes, without using any additional masks for defining specific oxide layer. The most important is that, after the NOI nonvolatile memory device is treated with the anti-fuse operation, the Gate and Drain of the NOI nonvolatile memory device still propose the switching characteristic the same to the traditional MOSFET, resulting from the oxide breakdown caused by a high electric filed merely occur in an overlapped oxide segment of the gate oxide layer.

The present application provides a method for manufacturing a semiconductor device including a merged active area (AA). The method includes forming a fuse gate structure over the active area; forming a device gate structure over the active area and adjacent to the fuse gate structure; and forming a contact plug coupled to the active area and extending away from the substrate. The fuse gate structure and the device gate structure are parallel and are formed over the active area.

The present application provides a method for manufacturing a semiconductor device including a merged active area (AA). The method includes forming a fuse gate structure over the active area; forming a device gate structure over the active area and adjacent to the fuse gate structure; and forming a contact plug coupled to the active area and extending away from the substrate. The fuse gate structure and the device gate structure are parallel and are formed over the active area.

A fuse component and a semiconductor device and a semiconductor device having the fuse component are provided. The fuse component includes an active region having a surface, a first fuse dielectric layer extending from the surface of the active region into the active region, a first gate metal layer surrounded by the first fuse dielectric layer, a second fuse dielectric layer extending from the surface of the active region into the active region, and a second gate metal layer surrounded by the second fuse dielectric layer. The first gate metal layer is electrically connected with the second gate metal layer.

A fuse component and a semiconductor device and a semiconductor device having the fuse component are provided. The fuse component includes an active region having a surface, a first fuse dielectric layer extending from the surface of the active region into the active region, a first gate metal layer surrounded by the first fuse dielectric layer, a second fuse dielectric layer extending from the surface of the active region into the active region, and a second gate metal layer surrounded by the second fuse dielectric layer. The first gate metal layer is electrically connected with the second gate metal layer.

A low-cost and low-voltage anti-fuse array includes a plurality of sub-memory arrays. In each sub-memory array, the anti-fuse transistor of all anti-fuse memory cells includes an anti-fuse gate commonly used by other anti-fuse transistors. These anti-fuse memory cells are arranged side by side between two adjacent bit-lines, wherein the anti-fuse memory cells in the same row are connected to different bit-lines, and all anti-fuse memory cells are connected to the same selection-line and different word-lines. The present invention utilizes the configuration of common source contacts to achieve a stable source structure and reduce the overall layout area, and meanwhile minimizes the types of control voltage to reduce leakage current.

Apparatuses, methods, and computing systems relating to three-dimensional fuse architectures are disclosed. An apparatus includes a semiconductor substrate, a fuse array on or in the semiconductor substrate, and fuse circuitry on or in the semiconductor substrate. The fuse array includes fuse cells. The fuse circuitry is configured to access the fuse cells. The fuse circuitry is offset from the fuse array such that the fuse circuitry is disposed between the semiconductor substrate and the fuse array, or the fuse array is disposed between the semiconductor substrate and the fuse circuitry.