A semiconductor device includes an electrode structure including electrodes stacked on a substrate and an insulating pattern on an uppermost electrode of the electrodes, a vertical structure that penetrates the electrode structure and is connected to the substrate, a first insulating layer on the electrode and the vertical structure, a conductive pattern that penetrates the first insulating layer and is connected to the vertical structure, an upper horizontal electrode on the conductive pattern, and an upper semiconductor pattern that penetrates the upper horizontal electrode and is connected to the conductive pattern. The conductive pattern has a first side surface on the vertical structure and a second side surface on the insulating pattern.

A differential memory cell array structure for a MTP non-volatile memory is provided. The array structure is connected to a source line, a word line, a bit line, an inverted bit liner and an erase line. After an erase operation (ERS) is completed, the stored data in the differential memory cells of the selected row are not all erased. That is, only the stored data in a single selected memory cell of the selected row is erased.

A three-dimensional memory device includes an alternating stack of insulating layers and word-line-level electrically conductive layers, a vertical layer stack located over the alternating stack, and including multiple levels of vertically interlaced drain select electrodes and drain-select-level insulating layers, a first insulating layer located between the alternating stack and the vertical layer stack, the first insulating layer having a thickness which is greater than a thickness of the respective insulating layers and the respective drain-select-level insulating layers, drain-select-level isolation structures laterally extending along a first horizontal direction such that drain select electrodes located at a same level are laterally spaced apart from each other by the drain-select-level isolation structures, memory openings vertically extending through the vertical layer stack, the first insulating layer, and the alternating stack, and memory opening fill structures located in the memory openings and including a respective vertical semiconductor channel and a respective memory film.

Embodiments relate to a semiconductor structure and a fabrication method thereof. The semiconductor structure has an array region and a peripheral region, and includes: a semiconductor substrate; a memory array structure positioned above the semiconductor substrate in the array region; a peripheral circuit structure positioned above the semiconductor substrate in the peripheral region; and a conductive connection structure positioned in the semiconductor substrate to electrically connect the memory array structure and the peripheral circuit structure. The semiconductor structure and the fabrication method thereof can effectively improve performance of a memory device.

According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.

A non-volatile memory device and its manufacturing method are provided. The non-volatile memory device includes a substrate and a plurality of first floating gates and a plurality of second floating gates formed on the substrate. The substrate includes a center region and two border regions located on opposite sides of the center region. The center region and two border regions are located in an array region. The first floating gates are located in the center region, and the second floating gates are located in one of the border regions. Each of the first floating gates has a first width, and each of the second floating gates has a second width less than the first width. There is a first spacing between the first floating gates, and there is a second spacing which is greater than the first spacing between the second floating gates.

According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of first members, and at least one first insulating member. The stacked body is provided on the substrate and includes a plurality of electrode layers. The electrode layers are stacked apart from each other in a first direction and extend in a second direction parallel to an upper surface of the substrate. The first members are provided in the stacked body and extend in the first direction and the second direction. The first insulating member is provided in the stacked body and extends in the first direction and a third direction so that the electrode layers are divided into a plurality of regions in the second direction, the third direction intersecting with the second direction and being parallel to the upper surface of the substrate.

A memory cell includes a substrate, a floating gate on the substrate, a control gate on the floating gate, a first dielectric layer between the floating gate and the control gate, an erase gate merged with the control gate and disposed on a first sidewall of the floating gate, a second dielectric layer between the floating gate and the erase gate, a select gate on an opposite second sidewall of the floating gate, a spacer between the select gate and the control gate and between the select gate and the floating gate, a source doping region in the substrate and adjacent to the first sidewall of the floating gate, and a drain doping region in the substrate and adjacent to the select gate.

A three-dimensional AND flash memory device includes a gate stack structure, a charge storage structure, a first conductive pillar and a second conductive pillar, an insulating pillar, and a channel pillar. The gate stack structure includes gate layers and insulating layers stacked alternately with each other. The first and second conductive pillars extend through the gate stack structure. The channel pillar extends through the gate stack structure. The charge storage structure is disposed between the gate stack structure and the channel pillar. The channel pillar includes: a first part and a second part connected each other. The first part is located between the charge storage structure and the insulating pillar. The second part includes a first region electrically connected to the first conductive pillar, and a second region electrically connected to the second conductive pillar. A curvature of the first part is smaller than a curvature of the second part.

A three-dimensional AND flash memory device includes a gate stack structure, a charge storage structure, a first conductive pillar and a second conductive pillar, an insulating pillar, and a channel pillar. The gate stack structure includes gate layers and insulating layers stacked alternately with each other. The first and second conductive pillars extend through the gate stack structure. The channel pillar extends through the gate stack structure. The charge storage structure is disposed between the gate stack structure and the channel pillar. The channel pillar includes: a first part and a second part connected each other. The first part is located between the charge storage structure and the insulating pillar. The second part includes a first region electrically connected to the first conductive pillar, and a second region electrically connected to the second conductive pillar. A curvature of the first part is smaller than a curvature of the second part.