Microelectronic devices include a stack structure of vertically alternating insulative and conductive structures arranged in tiers. The insulative structures of a lower portion of the stack structure are thicker than the insulative structures of an upper portion. The conductive structures of the lower portion are as thick, or thicker, than the conductive structures of the upper portion. At least one feature may taper in width and extend vertically through the stack structure. The thicker insulative structures of the lower portion extend a greater lateral distance from the at least one feature than the lateral distance, from the at least one feature, extended by the thinner insulative structures of the upper portion. During methods of forming such devices, sacrificial structures are removed from an initial stack of alternating insulative and sacrificial structures, leaving gaps between neighboring insulative structures. Conductive structures are then formed in the gaps. Systems are also disclosed.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the second transistors each include at least two side-gates, and where through the first metal layers power is provided to at least one of the second transistors.

A semiconductor storage device according to an embodiment includes: a stacked body in which a plurality of conductive layers are stacked via an insulating layer and which has a memory portion in which a plurality of memory cells are disposed and a staircase portion in which end portions of the plurality of conductive layers form a staircase shape. The staircase portion has three or more first sub-staircase portions ascending in a direction opposite to a direction toward the memory portion, and at least one first sub-staircase portion among the three or more first sub-staircase portions is divided into at least an upper staircase and a lower staircase by a difference in level larger than a difference in level of each stair of the first sub-staircase portion.

According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.

There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a cell stack structure surrounding a first channel structure and a second channel structure; a first source select line overlapping with a first region of the cell stack structure and surrounding the first channel structure; and a second source select line overlapping with a second region of the cell stack structure and surrounding the second channel structure. Each of the first source select line and the second source select line includes a first select gate layer overlapping with the cell stack structure, a second select gate layer disposed between the first select gate layer and the cell stack structure, and a third select gate layer disposed between the first select gate layer and the second select gate layer.

A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell for FinFET includes a fin, a control gate and a selective metal gate. The fin is on a top surface of a substrate, wherein the fin has two sidewalls and a top surface, and the fin includes a memory region and a logic region. The control gate is disposed over the fin of the memory region and covers the two sidewalls and the top surface of the fin, wherein the control gate includes a charge trapping layer and a control electrode, wherein the charge trapping layer is sandwiched by the fin and the control electrode. The selective metal gate is disposed over the fin adjacent to the control gate and covers the two sidewalls and the top surface of the fin. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and an opening. The pad structure may include a first stepped structure and a second stepped structure located between the first cell structure and the second cell structure. The first stepped structure may include first pads electrically connected to the first and second cell structures and stacked on top of each other, and the second stepped structure may include second pads electrically connected to the first and second cell structures and stacked on top of each other. The circuit may be located under the pad structure. The opening may pass through the pad structure to expose the circuit, and may be located between the first stepped structure and the second stepped structure to insulate the first pads and the second pads from each other.

Embodiments of 3D memory devices with a static random-access memory (SRAM) and fabrication methods thereof are disclosed herein. In certain embodiments, the 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes an array of SRAM cells and a first bonding layer, and the second semiconductor structure includes an array of 3D NAND memory strings and a second bonding layer. The first semiconductor structure is attached with the second semiconductor structure through the first bonding layer and the second bonding layer. The array of 3D NAND memory strings and the array of SRAM cells are coupled through a plurality of bonding contacts in the first bonding layer and the second bonding layer and are arranged at opposite sides of the plurality of bonding contacts.

A semiconductor memory device includes a memory cell array including a plurality of groups of memory cells above a substrate, the groups including a first group and a second group, each of the first and second groups including a first memory string and a second memory string, the first memory string including first memory cells that are disposed in a first layer, the second memory string including second memory cell that are disposed in a second layer above the first layer, and a controller configured to perform an erasing operation on the memory cells, the erasing operation including a verifying operation on the memory cells to determine on a layer by layer basis whether the memory cells failed to erase data stored therein.

A semiconductor device is provided. The semiconductor device includes an electrode structure that has gate electrodes that are sequentially stacked on a semiconductor layer, vertical structures that penetrate the electrode structure, and horizontal structures that extend in a third direction below the electrode structure. The vertical structures extend in a first direction and are spaced apart from each other in a second direction that crosses the first direction. Each of the vertical structures includes vertical channel patterns arranged in the first direction. The horizontal structure includes horizontal channel patterns. Each of the horizontal channel patterns is connected to at least three of the vertical channel patterns.