Provided is a method of forming a three-dimensional (3D) memory device including: forming a discharging layer and a stack structure on a buffer layer; forming vertical channel structures in the stack structure; forming an opening in the stack structure, wherein the opening includes two first trenches extending along a X direction and two second trenches extending along a Y direction, and the two first trenches and the two second trenches are separated from each other; forming an insulating layer on a sidewall of the opening; removing the discharging layer exposed by the insulating layer to form a cavity connecting the two first trenches and the two second trenches, thereby forming a ring-shaped opening; performing a gate replacement process to replace sacrificial layers of the stack structure by conductive layers; and filling an isolating material in the ring-shaped opening to form an isolating ring structure.

A semiconductor memory device includes a substrate, first conductor layers, second conductor layers, a third conductor layer, and an insulator layer. The substrate includes a first region, a second region, and a third region separating the first and second regions. The first conductor layers are above the first region. The second conductor layers are above an uppermost one of the first conductor layers. The third conductor layer is above the second region. The insulator layer is above the second and third regions. The insulator layer includes first and second portions. The first portion is above the third conductor layer at a height from the substrate greater than a height of the uppermost one of the first conductor layers and extends along a substrate surface direction. The second portion extends along a substrate thickness direction and contacts a surface of the substrate in the third region.

According to one embodiment, a semiconductor memory device includes first and second semiconductor layers and a first conductive layer. The first and second semiconductor layers extend in a first direction. The second semiconductor layer is stacked above the first semiconductor layer in a second direction intersecting the first direction. The first conductive layer intersects the first and second semiconductor layers and extends in the second direction. The first conductive layer includes first and second portions intersecting the first and second semiconductor layers respectively. A width of the first portion in the first direction is smaller than a width of the second portion in the first direction. A thickness of the first semiconductor layer in the second direction is larger than a thickness of the second semiconductor layer in the second direction.

A semiconductor device includes a stacked structure including a first region in which conductive layers and the insulating layers are stacked alternately with each other, and a second region in which sacrificial layers and the insulating layers are stacked alternately with each other, a first slit structure located at a boundary between the first region and the second region and including a first through portion passing through the stacked structure and first protrusions extending from a sidewall of the first through portion, a second slit structure located at the boundary and including a second through portion passing through the stacked structure and second protrusions extending from a sidewall of the second through portion and coupled to the first protrusions, a circuit located under the stacked structure, and a contact plug passing through the second region of the stacked structure and electrically connected to the circuit.

A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming peripheral circuitry in and/or on the first level, and includes first single crystal transistors; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming second level disposed on top of the second metal layer; performing a first lithography step; forming a third level on top of the second level; performing a second lithography step; processing steps to form first memory cells within the second level and second memory cells within the third level, where the plurality of first memory cells include at least one second transistor, and the plurality of second memory cells include at least one third transistor; and deposit a gate electrode for second and third transistors simultaneously.

An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.

An electronic device that comprises bitlines and air gaps adjacent to an array region of an electronic device is disclosed. The bitlines comprise sloped sidewalls and a height of the air gaps is greater than a height of the bitlines. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

A semiconductor storage device includes a memory cell array having a plurality of first conductive layers stacked in a first direction and a plurality of memory cells connected to the plurality of first conductive layers, a wiring layer, and an insulating layer between the memory cell array and the wiring layer and separating the memory cell array and the wiring layer in a second direction intersecting the first direction. The wiring layer includes a plurality of second conductive layers stacked in the first direction, each of the second conductive layers having a corresponding first conductive layer at a same layer, and a contact connected to at least a part of the plurality of second conductive layers and extending in the first direction.

A semiconductor device includes a substrate, a stacked body, a plurality of columnar semiconductors, a semiconductor layer, and a conductive portion. The stacked body is placed above the substrate. The stacked body includes a plurality of conductive layers stacked with an insulating layer placed therebetween. The plurality of columnar semiconductors pass through the stacked body. The semiconductor layer is placed above the substrate. The semiconductor layer is connected to bottoms of the columnar semiconductors. The semiconductor layer has a groove pattern in a region adjacent to the stacked body. The conductive portion fills the groove pattern and is in contact with a side surface of the semiconductor layer in the region. The conductive portion electrically connects the semiconductor layer to the substrate.

A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer and control circuits; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where each of the first memory cells include one first transistor, where each of the second memory cells include one second transistor, where at least one of the first or second transistors has a channel, a source, and a drain having a same doping type.