A method can be used to make a semiconductor device. A number of projecting regions are formed over a first semiconductor layer that has a first conductivity type. The first semiconductor layer is located on an insulating layer that overlies a semiconductor substrate. The projecting regions are spaced apart from each other. Using the projecting regions as an implantation mask, dopants having a second conductivity type are implanted into the first semiconductor layer, so as to form a sequence of PN junctions forming diodes in the first semiconductor layer. The diodes vertically extend from an upper surface of the first semiconductor layer to the insulating layer.

The present disclosure relates to an improved integrated circuit having an embedded flash memory device with a word line having its height reduced, and associated processing methods. In some embodiments, the flash memory device includes a gate stack separated from a substrate by a gate dielectric. The gate stack includes a control gate separated from a floating gate by a control gate dielectric. An erase gate is disposed on a first side of the gate stack and a word line is disposed on a second side of the gate stack that is opposite to the first side. The word line has a height that monotonically increases from an outer side opposite to the gate stack to an inner side closer to the gate stack. A word line height at the outer side is smaller than an erase gate height.

Disposed are a semiconductor structure, a manufacturing method thereof and a flash memory. The semiconductor structure includes a substrate, first isolation structures, a gate structure and an oxide layer. The first isolation structures define a first active area in a peripheral region of the substrate. The oxide layer is disposed on the substrate in the first active area and covered by the first isolation structures. The oxide layer and the first isolation structures define an opening exposing the substrate. The gate structure is disposed on the substrate in the first active area and includes a gate dielectric layer disposed in the opening and a gate disposed on the gate dielectric layer. The oxide layer is located around the gate dielectric layer. The width of the bottom surface of the gate is less than that of the top surface of the first active area.

Disposed are a semiconductor structure, a manufacturing method thereof and a flash memory. The semiconductor structure includes a substrate, first isolation structures, a gate structure and an oxide layer. The first isolation structures define a first active area in a peripheral region of the substrate. The oxide layer is disposed on the substrate in the first active area and covered by the first isolation structures. The oxide layer and the first isolation structures define an opening exposing the substrate. The gate structure is disposed on the substrate in the first active area and includes a gate dielectric layer disposed in the opening and a gate disposed on the gate dielectric layer. The oxide layer is located around the gate dielectric layer. The width of the bottom surface of the gate is less than that of the top surface of the first active area.

A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is self-aligned between the first and second devices and comprises a first filled portion and a second filled portion. The first fined portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. The self-aligned placement of the buried trench isolation allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.

A memory cell of a memory cell array includes a well region, a first doped region, a second doped region, a first gate structure, and a storage structure. The first doped region and the second doped region are formed in the well region. The first gate structure is formed over a first surface between the first doped region and the second doped region. The storage structure is formed over a second surface and the second surface is between the first surface and the second doped region. The storage structure is covered on a portion of the first gate structure, the second surface and an isolation structure.

The present disclosure provides a semiconductor device. The semiconductor device includes a silicide-containing field effect transistor disposed in a periphery region and a floating gate non-volatile memory device disposed in a memory region. The floating gate non-volatile memory device is free of silicide. The floating gate non-volatile memory device includes a second source, a third source, a fourth source, a second drain, and a third drain. The floating gate non-volatile memory device also includes a first floating gate electrode associated with the second source, the second drain, and the third source, and a second floating gate electrode associated with the second source, the third drain, and the fourth source. The second source is disposed between the first and second floating gate electrodes with a constant width. Each of the third source and the fourth source has a width larger than the constant width of the second source.

In some examples, an electronic device comprising an input ferroelectric (FE) capacitor, an output FE capacitor, and a channel positioned beneath the input FE capacitor and positioned beneath the output FE capacitor. In some examples, the channel is configured to carry a magnetic signal from the input FE capacitor to the output FE capacitor to cause a voltage change at the output FE capacitor. In some examples, the electronic device further comprises a transistor-based drive circuit electrically connected to an output node of the output FE capacitor. In some examples, the transistor-based drive circuit is configured to deliver, based on the voltage change at the output FE capacitor, an output signal to an input node of a second device.

A memory structure and its manufacturing method are provided. The memory structure includes a substrate, a tunnel dielectric layer on the substrate and a floating gate on the tunnel dielectric layer. The substrate has a source region and a drain region, and the source region and the drain region are formed on two opposite sides of the floating gate. The memory structure also includes an inter-gate dielectric layer on the floating gate and a control gate on the inter-gate dielectric layer. The memory structure further includes a doping region buried in the floating gate, wherein a sidewall of the doping region is exposed at a sidewall of the floating gate. Also, the doping region and the inter-gate dielectric layer are separated from each other.

A memory device includes a first well, a second well, a first active area, a second active area, a third active area, a first poly layer and a second poly layer. The first well is of a first conductivity type. The second well is of a second conductivity type different from the first conductivity type. The first active area is of the second conductivity type and is formed on the first well. The second active area is of the first conductivity type and is formed on the first well and between the first active area and the second well. The third active area is of the first conductivity type and is formed on the second well. The first poly layer is formed above the first well and the second well. The second poly layer is formed above the first well.