A vertically alternating sequence of unit layer stacks is formed over a substrate. Each unit layer stacks includes an insulating layer and a spacer material layer that is formed as, or is subsequently replaced with, a first electrically conductive layer. A 2×N array of stepped surfaces is formed. Each column of two stepped surfaces other than one column is vertically extended by performing a set of processing sequences at least once. The set of processing sequences includes forming a patterned etch mask layer and etching an unmasked subset of the 2×N array. One or more patterned etch mask layer has a respective continuous opening including an entire area of a respective 2×M array of stepped surfaces that is a subset of the 2×N array of stepped surfaces. Vertical stacks of memory elements are formed through the vertically alternating sequence.

A three-dimensional (3D) memory device is disclosed. The 3D memory device includes a memory stack, a semiconductor layer above the memory stack, a plurality of channel structures each extending vertically through the memory stack, and a source contact above the memory stack and in contact with the semiconductor layer. A semiconductor plug, in contact with the semiconductor layer, surrounds an end of one of the channel structures. The source contact is electrically connected with the one of the channel structures. At least a portion of the source contact is buried within the semiconductor layer.

Circuit structures to improve manufacturing yield in complex 3D circuits have a first stack of conductors and a second stack of conductors having memory regions and contact regions. Conductors of the first stack have stepped arrangement in the contact region to provide landing areas on the conductors. Connecting circuits connect the landing areas of conductive layers in the first stack to through-stack conductors in vias in the second stack, to connect to circuitry below the stack. The memory regions include arrays of vertical memory pillars. The connecting circuits include interlayer connectors contacting landing areas in the first stack, extending to patterned conductors over the first and second stacks. The patterned conductors can include links from interlayer connectors of the first stack to through-stack connectors of the second stack. The circuit structure can include a plurality of structural vertical pillars in the contact region of the first stack.

A semiconductor device may include stacks extended in a first direction on a substrate, separation structures extended in the first direction and respectively provided between the stacks, vertical channels penetrating each of the stacks, bit lines extended in a second direction crossing the first direction, each of the vertical channels being overlapped with a pair of the bit lines, and contact plugs connecting the bit lines to the vertical channels. Each of the stacks may include electrodes stacked on the substrate and at least two upper separation patterns dividing an upper one of the electrodes into several portions in the second direction. The vertical channels may be classified into a plurality of types, depending on a distance from one of the separation structures in the second direction, and each of the bit lines may be connected to all types of the vertical channels.

A semiconductor device may include stacks extended in a first direction on a substrate, separation structures extended in the first direction and respectively provided between the stacks, vertical channels penetrating each of the stacks, bit lines extended in a second direction crossing the first direction, each of the vertical channels being overlapped with a pair of the bit lines, and contact plugs connecting the bit lines to the vertical channels. Each of the stacks may include electrodes stacked on the substrate and at least two upper separation patterns dividing an upper one of the electrodes into several portions in the second direction. The vertical channels may be classified into a plurality of types, depending on a distance from one of the separation structures in the second direction, and each of the bit lines may be connected to all types of the vertical channels.

Embodiments of three-dimensional (3D) memory devices and methods for controlling a photoresist (PR) trimming rate in the formation of the 3D memory devices are disclosed. In an example, a method includes forming a dielectric stack over a substrate, measuring a first distance between the first trimming mark and the PR layer along a first direction, and trimming the PR layer along the first direction. The method also includes etching the dielectric stack using the trimmed PR layer as an etch mask to form a staircase, forming a second trimming mark using the first trimming mark as an etch mask, measuring a second distance between the second trimming mark and the trimmed PR layer, comparing the first distance with the second distance to determine a difference between an actual PR trimming rate and an estimated PR trimming rate, and adjusting PR trimming parameters based on the difference.

A method of forming a semiconductor device structure comprises forming a stack structure over a substrate, the stack structure comprising tiers each independently comprising a sacrificial structure and an insulating structure and longitudinally adjacent the sacrificial structure. A masking structure is formed over a portion of the stack structure. A photoresist is formed over the masking structure and over additional portions of the stack structure not covered by the masking structure. The photoresist and the stack structure are subjected to a series of material removal processes to selectively remove portions of the photoresist and portions of the stack structure not covered by one or more of the masking structure and remaining portions of the photoresist to form a stair step structure. Semiconductor devices and additional methods of forming a semiconductor device structure are also described.

A semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes in the memory cell region and the connection region, a plurality of channel structures passing through the plurality of gate electrodes and extending in a vertical direction in the memory cell region, and a plurality of pad layers extending in a first direction from each of the plurality of gate electrodes in the connection region. The plurality of pad layers is disposed in a stepped form in a second direction. The device further includes a plurality of dummy lines arranged in one row in the first direction between two pad layers adjacent to each other in the second direction and disposed apart from one another with a pad connection region therebetween in the first direction. The pad connection region overlaps two pad layers successively disposed in the first direction.

A semiconductor device including vertical structures on a substrate; and interlayer insulating layers and gate layers on the substrate, wherein the gate layers are sequentially stacked in a memory cell array area and extend into an extension area, the gate layers have pad regions having a staircase structure in the extension area, the first vertical structure has a surface facing the gate layers, the second vertical structure has a surface facing at least one of the gate layers, the first vertical structure includes a first core pattern, a first semiconductor layer, and a pad pattern, the second vertical structure includes a second core pattern and a second semiconductor layer, each of the core patterns includes an insulating material, and an upper surface of the second semiconductor layer and an upper surface of the second core pattern are farther from the substrate than the upper surface of the first core pattern.

A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.