In the memory structure, a pair of gate stack structures is on a first dielectric layer and separated from each other. Each of the gate stack structures includes a word line and a second dielectric layer. A third dielectric layer is on the sidewall of the gate stack structures. A pair of floating gates is between the gate stack structures. Each of the floating gates is on the third dielectric layer on the sidewall of the corresponding gate stack structure. The top surface of the floating gates is not higher than the that of the second dielectric layer. A fourth dielectric layer covers the first and third dielectric layers, and the floating gates. A control gate is on the fourth dielectric layer between the floating gates. A doped region is in the substrate beside the gate stack structures. An erase gate is above the control gate and the floating gates.

A nonvolatile memory device includes a substrate including a device isolation layer defining an active region, a floating gate and a selection gate arranged side by side at intervals of a first gap over the substrate, a coupling plate formed in the device isolation layer and overlapped with the floating gate, and a contact plug suitable for electrically coupling the coupling plate and the selection gate.

For erasing four-terminal semiconductor Non-Volatile Memory (NVM) devices, we apply a high positive voltage bias to the control gate with source, substrate and drain electrodes tied to the ground voltage for moving out stored charges in the charge storage material to the control gate. For improving erasing efficiency and NVM device endurance life by lowering applied voltage biases and reducing the applied voltage time durations, we engineer the lateral impurity profile of the control gate near dielectric interface such that tunneling occurs on the small lateral region of the control gate near the dielectric interface. We also apply the non-uniform thickness of coupling dielectric between the control gate and the storage material for the NVM device such that the tunneling for the erase operation occurs within the small thin dielectric areas, where the electrical field in thin dielectric is the strongest for tunneling erase operation.

A charge pump circuit includes a power switch, a first pull-low circuit, an output pull-low circuit, a first charge pump stage and an output charge pump stage. The power switch receives an enabling signal. The first pull-low circuit and the output pull-low circuit receive a pull-low signal. The first charge pump stage includes a first boost capacitor used to receive a first phase signal, a first transfer transistor, a first gate-control transistor and a first storage capacitor used to receive a second phase signal. The output charge pump stage includes an output boost capacitor used to receive a third phase signal, an output transfer transistor and an output gate-control transistor. The charge pump circuit generates voltages in an erasing operation, a program operation and a read operation according to the enabling signal, the pull-low signal, the first phase signal, the second phase signal and the third phase signal.

A single-poly nonvolatile memory cell includes a coupling capacitor, a cell transistor and a selection transistor. The cell transistor has a floating gate, a first source, and a first drain. The floating gate is coupled to an array control gate/source line through the coupling capacitor. The first source is coupled to the array control gate/source line. The selection transistor has a selection gate, a second source, and a second drain. The selection gate is coupled to a word line. The second source is coupled to the first drain. The second drain is coupled to a bit line.

A vertical semiconductor device may include a stacked structure, a channel structure and a lower connection structure. The stacked structure may include insulation layers and gate electrodes alternately repeatedly stacked. The stacked structure may be spaced apart from an upper surface of a substrate. The channel structure may include a charge storage structure and a channel. The channel structure may pass through the stacked structure. The lower connection structure may be formed on the substrate. The lower connection structure may be electrically connected with the channel and the substrate. A sidewall of the lower connection structure may include a protrusion disposed at a central portion of the sidewall from the upper surface of the substrate in a vertical direction. The vertical semiconductor device may have a high reliability.

A nonvolatile memory device includes a peripheral circuit including a first active region and a memory block including a second active region on the peripheral circuit. The memory block includes a vertical structure including pairs of a first insulating layer and a first conductive layer, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer spaced apart from each other on the second insulating layer, first vertical channels and second vertical channels. The second conductive layer and the third conductive layer are connected with a first through via penetrating the vertical structure, the second active region, and a region of the second insulating layer that is exposed between the second conductive layer and the third conductive layer.

A single poly NVM cell includes a first N-type well region and a second N-type well region spaced apart from each other by a P-type semiconductor layer, a first active region and a second active region disposed in the first N-type well region and the second N-type well region, respectively, a P-channel floating gate transistor including a floating gate disposed in the first active region, a P-type drain region disposed in the first active region, and a P-type junction region disposed in the first active region, wherein the floating gate extends to over the second active region, a P-channel read selection transistor including a read selection gate electrode disposed in the first active region, the P-type junction region disposed in the first active region, and a P-type source region disposed in the first active region, and an interconnection line connecting the first N-type well region to the P-type source region of the P-channel read selection transistor.

A nonvolatile memory device is provided. The device comprises a floating gate having a first finger and a second finger and an active region below the floating gate fingers. A first doped region is in the active region laterally displaced from the first floating gate finger on a first side. A second doped region is in the active region laterally displaced from the first floating gate finger on a second side. A third doped region is in the active region laterally displaced from the second floating gate finger and the second doped region.

Representative methods of manufacturing memory devices include forming a transistor with a gate disposed over a workpiece, and forming an erase gate with a tip portion extending towards the workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The erase gate is coupled to the gate of the transistor.